Bridging the Silos of the AI Data Center: My Journey Through Three Major Technical Conferences (ISSCC, DesignCon, and APEC)—and Advice for Engineers
Editors Note (5/31/26): I wrapped up ECTC, so this post reflects my experience when I originally wrote this before ECTC.
I added details about key substack articles I wrote along the way, and a link to an Asianometry video on superconducting electronics to get a flavor of what I worked on.
I’m currently attending ECTC, the flagship electronics packaging conference, from May 26-29 in Orlando, FL, to learn more about advanced packaging. Packaging represents the “container” that the chip sits within and interfaces with most HW domains.
I’ll be writing more on advanced packaging after this conference, but first, I want to take a moment in this post to reflect on the past three conferences I’ve attended, why I attended these, what I learned, and the advice I would give to engineers thinking of doing the same.
Why ISSCC, DesignCon, and APEC?
I recently had the unique opportunity to attend three major technical conferences back-to-back: ISSCC, DesignCon, and APEC.
I selected these specific conferences because, together, they develop a holistic, cross-functional view of the critical hardware challenges facing today’s AI data centers. Specifically, I wanted to understand the abstraction levels of the mixed-signal portions of the data center, which bridge two traditionally isolated domains: high-speed communications and power electronics.
But, there is a deeper reason why I attended these conferences. I anticipate the biggest technology risk in advanced electronic systems is not understanding the interactions amongst domains as domains become more tightly integrated. Many leaders throughout my conference travels urge the need for more cross functional awareness and that silos will no longer cut it. Many call for a “digital twin” as a simulation model that models all of these interactions. This is much needed, but just like any simulation, its important to develop a solid theory of these interactions to be able to interpret the simulation results and propose fixes.
To be completely honest, taking this on conference gauntlet was brutal—at least at first. But it got easier over time.
Not many people get the opportunity to do this. Companies are often hesitant to send engineers to conferences due to cost, inertia, or fears of intellectual property leaks. Because my circumstances were unique, I had to self-fund this journey.
Obtaining Interdiscplinary breadth: From Design, Applications, and Validation
The catalyst for this journey came after I was let go from my previous job. However, I build up a rich set of experiences leading up to it.
I gained a ton of interdisciplinary breadth while attempting to scale up superconducting computing from low level IP to EDA integration. Check out this video by Asianometry for a more in depth look into this technology.
One thing I noticed in any novel deep tech is that there is a HUGE disconnect between the potential for a technology from the financiers and its actual technological readiness from the bottom. I have my fair share of war stories dealing with the integration challenges when taking thinking from CMOS specialties and applying that to scale the EDA flow of a low impedance, highly coupled technology with unique first principles constraints.
In addition to superconducting electronics, I also have pretty extensive experience doing IC design for mixed signal, board design for power, and audio applications. Its quite a well-balanced range of activities that gave me a wholistic sense of the design process.
However, I was unexpectedly let go at my last job. I won’t go through all the details, but in short, it turned out not to be a good role fit for my skillset they brought me in for.
Since then, I’ve taken the time to go on a year long sabbatical to not only expand my own knowledge, but also to share it with others. I also wanted to provide a mental map for other engineers to become more T shaped or directors who want to bridge domains and need a technical reference point to understand engineers concerns across domains. The industry is screaming for cross-functional awareness, and I decided to cultivate it in myself.
The Strategy and Preparation
Before diving into the conferences, I took a few months for personal travel around the world in places in Europe and Asia, including key countries in the semi supply chain like Germany, Japan, Taiwan, and Singapore. I did cultural tours in each place to gain a sense of the historical and cultural influences, such as how key events such as the 228 incident influenced Taiwans politics today. It was a much-needed mental break from work, but it isn’t a lifestyle I’d want forever—the logistics and constant travel become a hassle.
When I returned, I committed to building my Substack. Over the previous year, I had accumulated a wealth of insights from technical textbooks and business books, including books on strategy, business, VC, and innovation. Check out some high level overviews for the some of the books I read and highly recommend:
Before I attended the technical conferences, I first started writing foundational, subsystem-level posts covering ADCs, PLLs, bandgaps, and AI accelerators from textbooks and key papers.
Building this technical baseline gave me the mental models I needed to absorb the conference material, starting with the toughest one of all.
1. ISSCC (International Solid-State Circuits Conference)
ISSCC is considered the “Olympics of chip design.” The overarching theme was “Advancing AI with IC and SoC Innovations,” focusing heavily on high-speed optical and wireline systems and associated high speed subblocks. It is heavily academic, dominated by professors and PhDs from top-tier universities.
Holding a Master’s degree myself, I’ll be honest: I would NOT recommend ISSCC for a first-timer. It was rough and felt like I was drinking from a firehose!
The plenary sessions covered a broad range of topics, including a talk given by Hope Giles, VP of PM at Apple, on why systems thinking and cross functional thinking are critical skills. Bernhard Wicht won a “Best book award” for his book “Design of Power Management Integrated Circuits” which is one of the best analog design books out there for not just PMIC design but also circuits that share the same blocks.
I purchased an All-Access Education Pass, which granted me entry to 10 tutorials and 6 forums/short courses, in addition to the technical sessions. While my previous writing on PLLs and ADCs helped me follow some of the technical sessions, there was still a massive gap in technical depth that made it hard to follow the advanced papers for long.
However, the tutorials and short courses were incredibly valuable. I attended deep dives on biomedical circuits, logic and memory, AI accelerators, and clocking/CDR techniques for wireline transceivers. The forums comprehensively covered both the power and high speed optical communications side of AI data centers, as well as a short course on optical communications. I also caught a fascinating panel on brain-machine interfaces featuring Jan Rabaey and the CEO of Neuralink.
As a result of this conference, I synthesized this firehose of information to write primers on optical communications and high-speed SerDes—creating the exact frameworks required to understand complex ISSCC papers.
2. DesignCon
DesignCon is the premier high-speed communications conference, famously themed around “where the chip meets the board.” While ISSCC is more posh and focuses on on-chip architectures, DesignCon is more laid back and focuses on the board-level implementation of high speed communications. It was a bit more industry-focused and accessible, though still a challenge coming the following week after ISSCC.
The event kicked off with an excellent tutorial by Dr. Mike Peng Li, a foundational figure in jitter and signal integrity. he has written extensively on jitter. Check out this chart of his that highlights all the possible sources of jitter:
The core technical sessions revolved around the practical challenges of handling 224 Gbps signaling and the scaling paths toward 448 Gbps. There was a huge variety of topics from co-packaged optics, power integrity, EMI mitigation, and AI applications in signal integrity. The massive expo hall was particularly enlightening, showcasing real-world in-rack and interconnect solutions. I learned about the existence of many lesser known companies in the high speed communications value chain such as Molex and Samtec.
The result of this experience allowed me to write my deep dives on high-speed signal integrity and silicon photonics. I don’t think every engineer needs to know every single source of jitter, just the fundamental concepts of DJ and RJ.
3. APEC (Applied Power Electronics Conference)
APEC is the flagship conference for power electronics. I kicked things off by attending three tutorials specifically focused on power delivery for AI data centers, as well as digital controllers for power electronics.
A massive portion of the conference focused on optimizing the data center power chain. Sessions broke down every major conversion step: 800V to 48V, 48V to 12V, 12V to 1V, and various intermediate bus voltage permutations. To be fair, the material felt a bit repetitive after a while; once you understand the underlying power architecture, many papers are just permutations of the same fundamental topologies. There was also a heavy focus on wide-bandgap semiconductors like GaN and SiC, as well as a focus on optimizing magnetics.
Check out this image from STMicroelectronic’s Booth on the power architecture:
I really appreciate the power domain because the board structure is a tightly coupled system. It forces designers to have a holistic sense of how every single component interacts. It’s an area you can nerd out on for an entire career because there is always a creative optimization trick to find.
This conference led to my article, “AI Data Center Power System: A Complete Overview.” It maps out the intricate tradeoffs between converter topology, footprint, and power delivery network (PDN) variables, explaining not just what the architecture is, but why it has to be that way.
Advice for Engineers
Navigating these conferences as an independent engineer taught me several lessons about career development, corporate dynamics, and learning strategies:
1. Try to get your company to pay first (and how to pitch it)
If you want to attend a conference, ask your company to sponsor you. Even if its for your own benefit, you should frame the request entirely around how the knowledge benefits the company. Sometimes management is simply unaware of the existence of these conferences, or might not see it as a big priority in your day job. Offer to give an internal presentation to your team afterward. This shows you want to distribute the value, rather than “hoarding” knowledge for your own resume.
2. Navigate corporate sensitivities carefully
Remember, your company’s name is printed on your badge. Have a clear understanding of who your competitors are before walking in. When networking, err heavily on the side of caution and silence. It is incredibly easy to let an innocuous statement about your current project slip—especially when alcohol is being served at networking events. Competitors can easily piece these details together into competitive intelligence.
3. If you self-fund, prepare in advance
If your company won’t pay and you decide to fund it yourself, make sure your finances are secure (I relied on index fund savings and 10 years of industry experience to comfortably fund this).
However, attending a few conferences is not something worth quitting your job over. If your company refuses to pay, it might be worth using vacation time and a bit of your own money. This money should be viewed as an investment in your own education.
Self-paying also has the added benefit of forcing you to take the conference more seriously. I found myself more actively engaged in the conferences, sitting near the front of most sessions, diligently taking notes. Its not the same experience as when a company pays for you to go because you have more skin in the game.
4. Consider if you’ll gain more value cheaper from purchasing and studying technical books
Conferences are excellent sources of truth for what is going on in the industry. With that said, conferences are probably not the first thing you should do until you have good fundamentals of the background technical material surrounding the conference. You might be better off going to an engineering library, picking up a few excellent technical textbooks, and thoroughly outlining them. I spent a year doing exactly that before I ever stepped foot in these conferences. That helped to close the knowledge gap with the conference material that builds up top of the fundamental textbook material.
Check out my post “Learning Analog/ Mixed Signal Design the efficient way” for my methodology that can apply to other technical areas.
5. Aim to become “T-Shaped”
As a near term career goal, try to attend one conference inside your core domain, and one that is interdisciplinary or adjacent to it. This builds a “T-shaped” skill set (deep expertise in one area, broad literacy across others). If you are looking for excellent interdisciplinary conferences, check out the ones I mentioned, but also consider:
VLSI Symposium (excellent to pair with a vacation to Japan or Hawaii)
DAC (Design Automation Conference)
SEMICON (various locations)
IEDM - IEEE International Electron Devices Meeting
6. Lean into the haze
Don’t be discouraged if you feel overwhelmed or hazy during the technical sessions. Even though I prepared quite diligently and my published posts look polished, I really felt incredibly out of my depth during the events at first. I needed weeks of breathing room afterward to digest the material. Take full advantage of the tutorials at the start of the week, and remember that you get access to the conference digest (papers and slide decks) afterward. Don’t put too much pressure on yourself to fully understand the technical sessions.
However, it does get easier over time because you’ll learn how to prepare a game plan to frame the material in the conference better.
Real growth happens when you sit slightly outside your comfort zone and process the gaps in your knowledge after the chaos subsides.
Conclusion
Its unfortunately very common that many companies nowadays are very execution focused and push the burden of responsibility on you to develop your own career. When I ran into organizational barriers trying to add value inside my company and let go, I decided to use the unemployment time as a “sabbatical” and add value to a broader audience.
Ultimately, the best path is to figure out how to add value to your current company in a way that is mutually beneficial. If you find yourself in a mismatched role, don’t just check out. Try everything in your power to add value to other around out first.
With that said, you’re ultimately responsible for investing in your own education. I, and many others, can provide this information, but cannot make you learn it if you don’t seek it out. Take coursera courses. Take advantage of engineering libraries. I would literally go to an engineering library and just casually browse through books and make notes on ones to dive deeper into later.
But just don’t hoard the insights for yourself. Find ways to share those insights with others so they might benefit as well. As they say, you learn 90% of the things you teach others.
Here are some of the articles I was able to produce as a result of these conference travels, including the methodology I used to self-study: