A Complete Deep Dive of Marvell GeSi Electro-Absorption Modulators and OMIB for Scaling Past 200Gbps
Co-Design Challenges: Physics Fundamentals, Packaging Real-Estate, Thermal/Power constraints in integrating XPU, HBM, and CPO, and potential use with NVIDIA DWDM
I’ll be doing a deep dive into a few topics centered around Marvell/Celestial AI’s Electro-Absorption (EAM) approach to scaling optical interconnects. The outline of my post is as follows:
Motivation behind Optical Interconnects
An Overview of GeSi Electro-Absorption Modulator (EAM)
Franz-Keldysh effect
Comparison with other external modulation options
Why Component Level Test Vehicles are Needed to Reduce Overall Integration Risk of 3D Heterogenous Integrated Packages
An Introduction to Marvell’s Photonic Link: A Fully Integrated Solution for XPU, CPO, and HBM
🔒Marvell / Celestial OMIB: Overcoming Edge Density Constraints
🔒Photonic Fabric Test Vehicle of EIC, PIC, and FAU w/ measurement results
🔒Example 3D Packaged Application: Photonic Fabric Memory Module
🔒Key Co-design Integration Challenges
🔒Thermal Management
🔒EAM Thermal Stability
🔒Package Thermal Steady State Characteristics
🔒Package Thermal Transient Characteristics
🔒Power Delivery Challenges
🔒How NVIDIA DWDM and Marvell’s EAM technologies can be powerful together
The research from this post comes from various Marvell’s papers from ECTC and their ISSCC forum presentation. I also incorporate relevant fundamental material from ISSCC short courses as well when developing the theory.
This post is aimed at more advanced understanding of some of the cross domain integration challenges that EAM is facing. Fortunately, I provide several references to several of my posts on advanced packaging, optical communications, and power architecture for all knowledge levels to understand the underlying fundamentals of Marvell’s Photonic Fabric Technology.
Before writing this, I wrote a similar deep dive on NVIDIA DWDM summarizing the challenges from both their ISSCC and ECTC papers, having attended both conferences myself. These posts come at a timely moment when NVIDIA recently announced they invested $2B into Marvell and Jensen announced at Computex that Marvell will be the next $1T company, causing the stock to soar.
I recommend you read my other NVIDIA post to put GeSi into its proper context and to read between the lines behind that stance:
Motivation behind Optical Interconnects
Scaling AI compute has many different bottlenecks: power delivery, thermal, and high speed interconnect density. Industry standard interconnects such as PCIe have limitations for the workloads AI compute demands. As a result, there is demand for high bandwidth, long reach interconnects that makes optical communications such an attractive option.
Within the optical domain, lasers themselves can be directly modulated (such as VCSELs) or light coming from lasers can be externally modulated. There are three primarily ways to externally modulate a light in the optical domain: Mach-Zehnder Interferometers (MZI), Ring, and Electro-Absorption. MZI modulates the phase of light travelling through two arms to cause destructive interference when recombined, and ring modulators act as band-stop filters for specific wavelengths of light.
I discuss these options in the following post:
GeSi Electro-Absorption modulators
EAMs operate by optical absorption of light through an electrically-controlled PIN junction at a single wavelength. A PIN Diode is a PN junction diode with an undoped intrinsic region to alter the PN diodes characteristics for the desired application, such as:
High-frequency RF switches / attenuators (Si, GaAs, InP),
High voltage tolerance by lowering the capacitance and thus increases breakdown voltage (GaN, SiC),
Photodetectors by converting optical signals to electric current through generation of Electron-Hole pairs (InGaAs, Ge)
In optical communications, EAMs device have a high bandwidth and a fairly compact footprint for CPO applications.
EAMs have a property called the Franz-Keldysh effect which is where the optical absorption in a semiconductor changes when an electric field is applied. This is shown as the black curve above shifting to the red curve when a bias voltage is applied. This allows a fixed wavelength light to be externally modulated at high speeds by quickly switching the absorption curve at that wavelength to affect how much light goes through.
As shown in the equations above, the extinction ratio can be calculated as the ratio of the exponentials of the absorption factors of the two states, and the insertion loss can be calculated as the exponential of the absorption at 0V. Higher extinction ratio and lower insertion loss is desired.
GeSi is a common material used for the intrinsic region. The GeSi is epitaxially grown on top of a flat surface that is polished with CMP. Light is routed through the GeSi which has a higher refractive index than the surrounding SiO2, thus causing total internal reflection through the device.
One common FoM is the the transmitter penalty (TP) which is a measure of the loss due to the modulation itself and combines both the IL and ER:
Here we see some example characteristics of Marvell’s EAM IL over wavelength over bias voltage and different temperatures. High temperature causes the IL to shift up and affect the absorption that each signal level sees.
This means that temperature stability and thermal management is crucial to ensuring that EAM devices can operating consistently within its intended environment. Sophisticated mixed circuit control circuitry is necessary to anticipate and correct for rapid temperature swings in the GPU and package.
While ring modulators face challenges with precise thermal control and MZI are quite large, EAMs offer a promising “middle range” alterative in high performance CPO applications. Advantages include:
Relatively small size
Good thermal stability
High speed
Low power
High optical bandwidth
However, there are a few downsides:
EAMs struggle from power handling because they absorb light, not phase shift it. There is an almost guaranteed 3dB loss from light passing through the EAM that must be accounted for in the link budget.
I believe the link budget is an extremely important concept that anyone investing in or designing optics needs to know because it affects which components in the supply chain can be successfully integrated in real systems. I dive more into link budgets here in the free section:
EAM devices are non-linear that, if uncorrected, affects the size of the individual eyes for PAM4 where the noise margin is governed by the smallest one.
To combat this, pre-distortion circuits are needed to pre-distort the four voltage levels so that the signal can be sent through the channel and recovered as linearly as possible.
EAM devices are difficult to reliably manufacture at scale. Growing the GeSi epitaxially requires a fairly flat surface and sophisticated means to control the crystal growth. High volume testing is needed to screen for KGD.
In short, GeSi offers several promising benefits for CPO, but does suffer from inherent device level challenges as well as circuit complexity challenges to control the characteristics of the PAM4 signal.
Why Component Level Test Vehicles are Needed to Reduce Overall Integration Risk of 3D Heterogenous Integrated Packages
There are several excellent research works being performed across the industry and academia on components that comprise integrated 3D packaging solutions:
Different substrates: organic, silicon, glass
Different bridge option: LSI, embedded bridge
Interconnect options: C2, C4, and Hybrid bonding
Different integration options: 2.1D, 2.3D, 2.5D 3D, 3.3D, 3.5D.
Different optical component integration and waveguide routing options in each substrate
Ideally, each component (whether that be chip-level IP or mechanical components) should have clearly defined datasheets (such as loss over frequency, CTE, etc) with validation/yield data backing it up to minimize final assembly risk. When system integrator components buy parts, they do a competitive analysis by reading multiple datasheets, selecting a part, and expecting the device to perform within those given operating conditions. Hybrid Bonding is an example where that is NOT the case, and is only used in specialized cases behind NDAs.
However, the current AI market is demanding innovative higher performance components that don’t have defined datasheets yet. Its not always possible for promising solutions to be fully vetted before they can be used, because by then the next higher performing part is right around the corner.
For tightly integrated AI Compute packages, innovative yet unproven components can cause integration risk. Parallel optimization efforts of innovative solutions are needed to make sure that block performance improves along with the whole system.
One major issue are the cross-domain interactions across interfaces. EAM have thermal stability challenges between the optical and thermal interface, and high speed signals can suffer from Power-supply induced Jitter (PSIJ) between the power and signal integrity interface. These cross domains interactions can be tricky to anticipate if each component is optimized in isolation from each other and not caught early on.
To minimize final integration risk, new IP is proven out on test chips or demonstration vehicles on smaller subsystems. These IP provide system integrator companies valuable data to assess integration risk and provide several options to choose from. Major tech companies often identify several “fallback” options of sockets within their product, whether that be consumer electronics or hyperscalers, so that they can protect their supply chain from one bad component and minimize of risk of integrating new ones.
I say this because I have many war stories of scaling superconducting computing from standard cells to VLSI integration, where tapeouts were mainly structured around integration risk reduction: before using newly invented logic gates in higher level P&R flows, they need to be taped out on test chips with data to show that they are at least functional. They might not be fully optimized to “gate” usage at high level assemblies, but optimization can be done in parallel alongside tool development.
Though it sounds exciting from the outside, its not always a fun process on the inside as it can feel chaotic. In hindsight, you do learn a lot in the process.
Marvell’s Photonic Link: A Fully Integrated Solution for XPU, CPO and HBM
Now I will comprehensively review Marvell’s/Celestial AI’s approach to CPO.
Marvell is trending toward 3D integration with the EIC stacked on top of the PIC with a silicon bridge connecting XPU and PIC. Their Photonic Fabric Approach has the following three components:
PFLink™: a chiplet optical link that supports supporting UCIe-A interfaces with 14.4 Tbps BW and reach > 50 meters.
PFSwitch™: a system-in-package switch enabling all-to-all XPU connectivity.
OMIB™: an optical multichip interconnect for large package integration.
However, this approach presents several co-design challenges along several domains:
Packaging Real Estate: One issue with CPO is the edge density (or Beachfront) of the ASIC. In AI Compute heavy GPUs, HBM, CPO, and the power delivery network want to be as close to the ASIC as possible to minimize loss in high-speed and high-power signal. This creates a real estate tradeoff of which components should remain close to the ASIC depending on what is being optimized. GPUs need HBM as close as possible for training AI models, while CPUs and other ASICs may not have as strict memory requirements.
Power Integrity: Power needs to be delivered to the I/Os in the die interior. This requires enough power density and a low enough impedance over the frequency range of expected transients. Vertical power delivery is proposed to support this, but there needs to be enough space for TSVs and decoupling capacitors close enough to the ASIC to provide the power density at a low impedance at the transient frequency.
Thermal Stability: Steady state and transient thermal simulations are needed to quantify the thermal proximity of the characteristics of the EAM, as well as how the EAM characteristic shifts in response.
After the paywall, I will dive deeper into Marvell’s 3D Photonic Fabric implementation and solutions to these three challenges from their ISSCC forum and ECTC papers. I’ll also cover a slide that caught my eye in how NVIDIA DWDM and Marvell EAM can potentially synergize with each other.
Here are several of my other posts that give you a fundamental understanding of the key tradeoffs in each of these areas:
