Advanced Packaging Co-Design: The Thermodynamic and Mechanical Constraints of High Power GPUs
Key packaging constraints and challenges for High Power GPUs - thermodynamics, stress/strain, warpage, failure mechanisms, and warpage mitigation
Editors Note (6/23/26) - The last half of the post will be paywalled. Before each paywall, I link several of my other posts in domains adjacent to the topic you are reading to give you a well rounded flavor of the areas adjacent to packaging.
At ECTC 2026, TSMC noted that many package designers are being too aggressive with their package designs and that a lot of communication is needed to balance the design performance with the manufacturing and reliability constraints of the package.
This post helps reduce that communication overhead.
In this post I’ll be diving into the key mechanical and thermal factors needed for co-designing advanced packaging for high power. The outline of this post is as follows:
I will explain the current I-shaped paradigm in most technology companies and why engineers will need to embrace T-shaped skillset to effectively co-design tightly integrated systems
I’ll discuss the key challenges that GPUs are placing on both the package and circuit side
Then I’ll discuss two fundamental concepts and associated material properties for successful co-design of sub-components with advanced packaging:
Thermodynamics, including the three sources of heat transfer and thermal resistance
Stress-strain and associated material properties such as CTE
Then I’ll describe the:
🔒Three main sources of warpage
🔒Four common failure modes
🔒Challenges with modelling cross coupling failure modes
🔒Last, I’ll discuss a few warpage mitigation options
The research from this post comes from both from my conference experience at ECTC and the book “Hybrid Bonding, Advanced Substrates, Failure Mechanisms, and Thermal Management for Chiplets and Heterogeneous Integration” (2025). I found this book to be a useful mix of both high-level fundamental overviews of advanced packaging and current in-the-weeds academic research on key areas related to packaging.
I previously wrote a masterclass post on the fundamentals of advanced packaging that covers what packaging “is”. This post builds off that by covering the physics dimension when it comes to CTE, warpage, and failure modes. I recommend you read that post along side this one to build a more complete view of advanced packaging.
First I want to describe what I believe effective hardware co-design requires.
A New Approach for Hardware Co-Design: The T Shaped Engineer
Currently, most engineers at major tech companies operate in the “I” shaped paradigm where engineers are highly specialized in their field of choice, and interface with other engineers through requirement specifications and handoff at interfaces.
As systems start become more tightly coupled across domains, many leaders are calling for more cross domain awareness and co-design. However, I believe that most engineers in the “I” shaped paradigm treat co-design as more frequent and earlier meetings.
I believe that effective co-design requires you to become more ‘T” shaped, that is, depth in one domain and breadth in others. This requires you to build a semi-independent knowledge base of high level concepts in other domains to be able to intuitively assess how factors from your domain affect others. This allows you to anticipate issues and ask key questions from domain experts early on.
Becoming T shaped is actually quite difficult to do in an I shaped paradigm, both cognitively and organizationally. Vikram Sekar described these challenges best when he gave career advice because often times, it might be possible to “step” on adjacent teams who are CTA.
I totally understand this, and I’m not saying you should ignore your orgs politics. In any case, here is my blueprint for people who want to become more “T” shaped:
Ground yourself in fundamental tradeoffs in silos adjacent to your domain of expertise
Effective co-design across multiple domains requires you to first ground yourself in the fundamentals of domains that relate to each other in some way. This requires deep work to analyze the technical fundamentals in domains adjacent to your own.
For me, the bulk of my co-design posts revolve around four interconnected domains in hardware:
On-chip mixed signal (SerDes architecture, ADC, PLL)
High speed communications (Optical, high speed wireline, and signal integrity)
Power integrity / management
Advanced packaging
Each specialty has their own unique set of tradeoffs, such as:
Gain vs bandwidth in Analog
Interconnect distance vs BER in SI
Switching frequency vs ripple vs loss in Power
Substrate area vs bump stress in Packaging
Understanding the fundamentals in each domains is not an easy process because it requires to you sort through domain specific knowledge from experts and try to extract out the important insights. I found that the tutorials at the beginning of the conferences are excellent at providing a framework to understand more complex conference material that build upon the tutorial material; these are what the tutorials are specifically made for. That way, when I read dense technical papers or conference digests, I can efficiently filter through information that doesn’t matter. I find that the bulk of the writing in conference papers is really dancing around the nuances of previous works while making claims of proposed solutions.
I’m not saying you should become an expert in domains outside of your own; that is overkill for practical purposes. However, I do think you should work backwards to figure out what baseline knowledge you need to understand more domain-specific knowledge from other people.
Understand how adjacent domains couple together
Then, after understanding tradeoffs in each domain, try to understand how effects from each domain “couple” to other domains. Based on my previous writing, these are some interactions I can think of off the top of my head:
Power supply induced jitter and crosstalk lower BER of the signal path
Fast current transients in AI workloads cause localized joule heating that can worsen reliability
Ring modulators in optical communications are sensitive to thermals that need to be corrected with heater feedback loops
Understanding interactions is quite tricky that I admittedly don’t really understand fully quite yet and am trying to understand better myself.
My advice: start small and teach others
As a start, I recommend people first ground themselves in ONE field. Power and packaging are excellent interdisciplinary fields to start for anyone involved in semiconductors in anyways. I have several posts that provide a good starting point.
Then, to really test if you have the knowledge, try to teach it to others, whether that be through writing or a seminar. This way, others can mutually benefit from the insight in your own process of becoming more T shaped. It’s quite easy to fool yourself in thinking you know something from reading someone’s article until you go and sit down and explain that topic to another person.
The Co-Design Problem: High Power Density Stresses the Package
GPU roadmaps are projecting a huge increase in computational power that comes with higher performance requirements, including:
High power usage. GPUs draw huge current density that is lost in the PDN and dissipates heat.
High transient response. The critical frequency band of AI workload transients is between ~0.1-10 MHz, and the PDN needs to provide low enough impedance at these frequencies to meet the on-chip droop specs. This is typically done by placing localized decoupling capacitors as close to the chip as possible.
Large Area. More GPUs per package increase the package area that increases the Distance to the Neutral Point (DNP).
To meet these performance demands, innovations are both needed on the package and circuit design side.
On the circuits side, much work has been done on optimizing specialized power conversion topologies such as multi-phase buck/TLVRs at the PoL and LLC DCX for the IBC. I dive deep into these fundamentals of the circuit architectures in more detail:
On the packaging side, there are several well established failure mechanisms and integration techniques. I briefly touched upon these in these posts:
The issue with high power is that they stress the package, enhance the already established failure mechanisms, and opens up possibilities for new ones. Large BGAs with up to 2000 - 6000 balls face mechanical challenges with heavy heat sinks and continuous vibration.
Lets dive deeper into important packaging considerations.
Fundamental Thermal and Mechanical Concepts: Thermodynamics and Stress-Strain
Co-design of the high power with the package involves knowledge of fundamental concepts in thermodynamics and stress-strain. These are pretty well known to people in those domains and I realize there’s a lot more depth underneath these equations I am simplifying.
As an EE myself who is more specialized on the circuit side, I’m framing these as high level mental models for people outside of these domains to have a first order understanding of the mechanical and thermal effects of packaging.
Likewise, if you are very familiar with these but not familiar with those concepts on the electrical side like signal integrity, power electronics, or the intricacies of high speed SerDes, well, lucky for you, I have mental models on those on my Substack as well that are linked throughout this post.
The Three Sources of Heat Transfer
Conduction
Conduction is heat transfer within a stationary solid, liquid or gas due to temperature differences. Energy is “diffused” from more energetic regions to less energetic particles.
Conduction is governed by Fourier’s law:
where
q′′ is the heat transfer per unit area (W/m2 )
k is the thermal conductivity of the material (W/m K)
dT/dx is the temperature gradient (K/m)
Common values for thermal conduction range from:
0.024 (air),
~0.2 - 0.35 (for epoxy, polymide, and FR4)
120 (silicon)
390 (copper)
Conduction matters when dissipating heat from:
The GPU - Rubin generates 1,800W to 2,300W per GPU
Joule heating in the interconnects - this is self-heating due to IR drop that increases as current density increases
Convection
Convection refers to heat transfer between a surface and a moving fluid at different temperatures
Convection is governed by Newtons laws of cooling:
where
q′′ is the heat transfer per unit area (W/m2)
h is the convective heat transfer coefficient (W/m2 K)
Ts is the surface temperature of the solid (K or ⁰C)
Tinf is the temperature of the surrounding fluid far form the surface (K or ⁰C)
Convection can be classified either as free (such as hot air rising from a heater) or forced (such as cooling a CPU with a fan).
Common values for convective heat transfer coefficient include:
Free: 2 - 25 for gasses and 1000 for liquids
Forced: 25 - 250 for gasses and 100 - 20,000 for liquids
Convection cooling can be facilitated through the use of heat sinks, liquid cooling or immersion cooling with single and two phase variants.
Radiation
Radiation is the transfer of thermal energy through EM waves without a need for a medium. It is governed by:
where
E is heat transfer rate of emission (W)
ε is the emissivity of the surface (between 0 to 1)
σ is the Stefan-Boltzmann constant (5.67e-8 W/m2 K4)
A is the surface area of the radiating body
T_s is the absolute temperature of the surface (K or ⁰C)
Compared to conduction and convection, radiation is not a primary heat transfer mechanism for ground based AI data centers, but could potentially be a dominant heat mechanism for space based AI data centers. We’ll see how that plays out.
Note that radiation also includes the absorption of incident radiation, so the net heat transfer depends on the balance between the inflow and outflow of radiation.
Conduction and convection must be in balance for ground based AI data centers
Fundamentally, for a GPU to maintain a thermal equilibrium below a threshold temperature, the conduction and convection equations must be in balance with each other for the cooling system to handle the heat dissipation of the GPU and subsystems.
Of course, there are many other factors such as boundary conditions, unique material properties, and CPU loads that are important and must be taken into account. If, for whatever reason, the heat removal becomes a bottleneck of GPU performance, then tricks need to be played on the SW side to manage the workload until the cooling or packaging system is able to catch up.
Thermal Resistance
Thermal resistance quantifies the opposition to heat flow at any two points where there is a temperature difference. It is given by
where
R_th is the thermal resistance (K/W or ⁰C/W)
∆T is the temperature difference between two points (K or ⁰C)
q is the heat transfer rate (W)
Thermal resistance is a convenient first order approximation because it almost resembles an Ohms law analogy to heat transfer, with analogous parameters:
Electrical current is the heat transfer rate
Electrical resistance/conductivity is thermal resistance/conductivity
Electrical potential is the temperature
Heat sink fins can be modelled approximately using this model to estimate heat transfer. Of course, this approximation is valid if the thermal “circuits” are contained within a lumped approximation, where the heat flow is uniformly distributed in confined materials. Anything that is distributed or highly coupled will require sophisticated modelling.
Stress-Strain
All materials with a PCB stack experience strain / material deformation under some kind of loading. There are two major categories of materials:
Ductile material - A material that initially deforms linearly as more stress is applied, then after a certain threshold, it undergoes plastic deformation over a wide range until it ultimately fails. This is the dynamic when you pull hard taffy or gum. Most metals fall into this category.
Brittle materials - Brittle materials show a steep linear curve with a sharp fracture at the top. Glass falls into this category.
For ductile material, the left most region is governed by Hookes law which describes material deformation in the elastic region. It is given by
where
σ is the average normal stress across a cross section area of a material
ε is the average normal strain, give by (L - L0) / L0
E is the modulus of elasticity (or Youngs modulus)
On the right side of the linear region, the material starts deforming and ultimately fails to a fracture. Of course, we hope that packaging materials don’t enter this region, but performance requirements can make it difficult to design around this.
Another form of strain, shearing, changes the angle between two normally perpendicular lines of a material. It is given by:
Bumps in between package layers experience both shearing and compressive / tensive forces.
There are a few material properties that matter:
Youngs modulus - Describes the ability for a material to resist deformation when subjected to stress. Typical values include:
6 for underfill epoxy
8 - 22 for FR4
131 for silicon
132 for copper
Poisson’s ratio - the ratio of the strains in the axial direction and the lateral direction. The max value is 0.5. Typical values include:
0.1 - 0.14 for FR4
0.28 Silicon
0.35 for copper
Creep - a time dependent permanent deformation of a material under a constant load or stress at a constant temperature. Creep is common at elevated temperatures.
Stress relaxation - a gradual decrease in stress by a material under a constant strain over time.
Viscoelasticity - a nonlinear, hysteretic curve to loading and unloading where a material recovers its shape over time after unloading
Viscoplasticity - when a material suffers permanent, rate-dependent plastic deformation that does not recover
Viscoplasticity is important when describing the behavior of solder since it is subject to strain and creep deformation.
One popular viscoplasticity model of solder is the Anand model that governs the rate of change of the inelastic strain. It takes multiple effects such as strain rate sensitivity and deformation resistance into account.
Coefficient of Thermal Expansion (CTE)
CTE is perhaps one of the most important and most talked about material properties for packages because it describes material behavior at the interface of thermal and mechanical properties.
CTE is a form of material “strain” where an increase in temperature causes the material to expand, and a decrease causes it to contract. It is given by:
where
εth is the strain due to temperature with no mechanical load
α is the coefficient of thermal expansion
∆T is the change in temperature
Common CTE values include:
2.6 for silicon
17 for copper
20, 70 for epoxy
FR4:
10, 15 in plane
65, 180 in z-axis
For any given package size, material with a higher distance from the neutral point will experience higher deformation since it elongates / contracts more, thus increasing the stress on solder joints in that area.
Warpage
Now that I've established some thermal and mechanical fundamentals, we can discuss how these play a role in warpage, and failure modes after the paywall.