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A Complete Deep Dive of NVIDIA DWDM Co-Packaged Optics for Scaling beyond 200Gbps
Key physics constraints and architecture challenges for scaling data rates in DWDM - ring modulator physics, clocking, CW-DFB Laser, and package…
Jun 23
•
Chad
11
2
Advanced Packaging Co-Design: The Thermodynamic and Mechanical Constraints of High Power GPUs
Key packaging constraints and challenges - thermodynamics, stress/strain, warpage, failure mechanisms, and warpage mitigation
Jun 17
•
Chad
8
2
A Masterclass on Advanced Packaging and Heterogeneous Integration
From 2D to 3.5D, a teardown of 2.5D CoWoS (TSV, RDL, Bump/pillar) and emerging trends (Glass, Panels, Bridges in Organic Substrate, and Hybrid Bonding)
Jun 9
•
Chad
17
3
ECTC 2026: The Multi-Physics and Packaging Bottlenecks of Next-Gen AI Clusters
Key challenges in Advanced Packaging, Reliability, CPO, and Multiphysics simulation
Jun 2
•
Chad
9
4
May 2026
Bridging the Silos of the AI Data Center: My Journey Through Three Major Technical Conferences (ISSCC, DesignCon, and APEC)—and Advice for…
Editors Note (5/31/26): I wrapped up ECTC, so this post reflects my experience when I originally wrote this before ECTC.
May 26
•
Chad
5
3
The Cognitive Offloading Trap: How AI Breeds Overconfidence (And How to Overcome It)
The dangers of offloading human cognition to AI and how intellectual agency is important
May 22
•
Chad
2
1
2
Silicon Photonics Architecture: Quantifying Link Budgets and Optical Nonidealities
Silicon photonics is one of the hottest and fastest moving markets to address high speed data demands in co-packaged optics (CPO) in AI data centers.
May 20
•
Chad
8
4
April 2026
From Atari to ChatGPT: The Technical and Corporate Forces Shaping Frontier AI
How the intersection of scientific ambition, commercial urgency, and safety research birthed the modern scaling era.
Apr 29
•
Chad
4
3
A Comprehensive Overview of High-Speed Optical Communications
Scaling high-speed data movement from IM-DD to CPO/Silicon Photonics/Coherent
Apr 14
•
Chad
87
16
APEC 2026: A Complete Overview of the AI Data Center Power System
Why Power Delivery Network Constraints Are Pushing AI Power Delivery Vertical at the Point-of-Load
Apr 6
•
Chad
46
5
11
March 2026
Pushing the Speed Limit: Designing SerDes Transceivers for the 224 and 448Gbps Scaling Era
An architectural analysis of DSP-driven SerDes datapaths, current-steering nonidealities, and the multi-phase clock constraints breaking modern wireline…
Mar 23
•
Chad
18
5
High-Speed Signal Integrity: Physical Impairments and Equalization Architectures
How signal integrity influences complexity of modern wireline transceiver architecture from first principles
Mar 17
•
Chad
14
5
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