While a lot of attention is being drawn to the current HBM4 shortage, this post will focused on the practical technical challenges in scaling HBM5 performance.
I will discuss the following signal integrity and co-design challenges in HBM5 based on SK Hynix and KAIST’s ECTC 2026 papers:
Introduction to Signal Integrity trends from HBM1 to HBM5
🔒Jitter component tree and descriptions of key sources of jitter for short, high-speed interconnect:
🔒Echo
🔒SSC / SSN
🔒PSIJ
How SK Hynix quantifies transmission line effects in high-speed HBM5 data lines
🔒Fundamentals of Transmission Lines
🔒Proposal for two operating regions: RC and LC dominated regimes
🔒Design of Experiments results for echo jitter across interconnect lengths and dimensions
🔒KAISTs SI/PI co-analysis framework for Chiplet (UCIe)-based GPU-HBM Interconnect for PSIJ
🔒Shoreline density limitations for a 4 layer wide-IO and chiplet interconnect scheme
🔒Calculating power-supply induced jitter (PSIJ) from SI, PI, SSC, and jitter sensitivity / amplification
🔒BONUS: “The Brain” - 3D Custom HBM and current status among TSMC, SK Hynix, NVIDIA, and Samsung from ECTC 2026
This post is heavily influenced by the ECTC session 11, “Signal Integrity Design for High-Speed Interfaces” as well as my experience at DesignCon 2026 I was personally in attendance for.
This will be more of an advanced deep dive, but grounded in fundamentals. I structured the post to start with baseline EE concepts and building a framework to understand the complexity of multi-layer SI/PI co-design. I have a post that covers the fundamentals of signal integrity that forms the foundation of the issues I discuss:
I encourage you to read through my backlog of knowledge and challenge you to take away one new in-depth concept. Even if the technical material doesn’t stick, I still hope you come away with an appreciation of the challenges that keep HBM and SI engineers up at night.
Note that I am not a signal integrity person. However, I immersed myself into the SI world by attending DesignCon 2026 with an RF / Microwave lens upon which to analyze high-speed signal integrity effects. It was clear upon reading these papers that memory and SI engineers do not speak the same language as RF people do, but they describe the same effects from their point of view.
I personally think that at increasingly faster data rates, there will be a convergence of the knowledge among RF / microwave and signal integrity domains. I aim to bridge this gap of understanding.
SK Hynix - High speed HBM roadmaps
High bandwidth memory (HBM) is a critical component for AI training workloads that stores everything involved in AI computation from model weights, gradients, optimizer states, and activations. HBM connects multiple DRAM dies vertically using TSVs to maximize memory density in the given footprint. These DRAM dies are placed as close to the GPU as possible to maximize the data throughput to overcome the Von-Neumann bottleneck.
In this SK Hynix roadmap presented at ECTC 2026, there are a few performance scaling trends along HBM generations:
Between HBM1 and HBM4, the datarate per DQ increased linearly from 1Gb/s to 11.7Gb/s
Along those generations, the signal rise time and unit interval (UI) scaled inversely proportional to the total data rate per DQ
Between HBM3E and HBM4, there is a stairstep jump in the the total bandwidth by 2.5x, primarily driven by doubling I/O per cube from 1024 to 2048.
To keep with up AI workload demands, HBM5 expects a 20-30 Gbps per DQ range using state-of-the art interposer technologies such as the Chip-on-Wafer-on Substrate (CoWoS-L and CoWoS-R).
At those data rates, HBM is running into co-design challenges along the signal integrity, power integrity, and thermal domains. At ECTC, there are three high-level trends I noticed amongst three papers:
Jitter due to Transmission Line Effects
SK Hynix notes that significant transmission line effects were not observed for previous HBM generations with a data rate of under 10 Gbps per DQ and approximately 6-mm-long interposer interconnects.
However, at 30Gbps rates, advanced packaging interconnect technologies exhibit distinct lossy transmission line characteristics and must be accounted for.
Normally, transmission lines are terminated with equivalent impedances to avoid reflections. However, termination resistors cannot be reasonably employed for terminating 1000+ I/O in HBM as this would lead to high thermal penalties and static power dissipation. This leads to additional signal integrity challenges that will be discussed.
From “Wide-and-slow” to UCIe
Another challenge is edge density limitations of I/O. Doubling the number of I/O pins results in excessively large physical layer (PHY) footprint on the silicon. The number I/O is fundamentally constrained by the metal pitch, # of layers, and the area dedicated to ground rails to control crosstalk.
To scale the number of I/O, KAIST is investigating the performance impact of going from wide-and-slow I/O toward higher-speed SerDes lanes in Universal Chiplet Express (UCIe) standards.
KAIST notes that in chiplet-based GPU-HBM based on UCIe, eight D2D modules are utilized, with each module consisting of 64 Tx and Rx at 32Gb/s each. A total of 512 Tx and Rx supports 2 TB/s for read and write directions.
With a faster, more compact PHY, more I/O them can fit in the HBM shoreline to increase the data throughput.
PDN for 3D stack
Another co-design challenge is how the TSVs in the HBM stack affect thermal characteristics.
This paper evaluates the thermal and IR drop characteristics of different TSV configurations. Here we see how each component is modelled as an array of unit cells in a grid structure with an equivalent RLC circuit model.
Though I think this paper is important for effective co-design, especially when it comes to modelling PDNs for PSIJ, I have left the analysis out of this post for now to focus on signal integrity challenges from the first two papers.
Key sources of jitter in high-speed, low-voltage parallel lines
After the paywall I will cover key sources of jitter and the challenges that HBM faces in more depth. In the meantime, checkout a few of my other posts.
