Editors note (6/1/26) - Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

I am removing …

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Editors note (6/1/26) - Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

Before each paywall, I add links to additional posts I wrote so you can get a wholistic sense of how systems that interface with PLLs work.

This post covers the following topics:

• High level design principles

• An Intuitive Look into Type I and Type II Phase Locked loops

  • Type 1 PLL: XOR and RC LPF

  • Type 2 PLL: Charge Pump

  • Bode Plots Comparison for Type I and II PLLs

• The Transfer Function of the type II PLL

• 🔒Common transistor level implementations of type II PLLs

  • 🔒Phase-Frequency detector

  • 🔒Charge Pump

  • 🔒Voltage Controlled Oscillator

    • 🔒LC Oscillator

    • 🔒Current Starved Ring oscillator

• 🔒Important considerations: Phase Noise and Jitter

• 🔒A high-level look into the Fractional-N Synthesizer

A modern chip is like a finely tuned orchestra. Each member of the orchestra knows their role and what notes to play, but needs to know when to play them. The conductors role is to align musicians to a shared interpretation of tempo.

Imagine if there was no conductor; musicians don’t know when to play, so the orchestra gets out of sync really quickly as each person plays to their own tempo.

This is the role PLLs play in circuits: as the “conductor” that produces a clock to keep blocks synchronized to a common reference. PLLs help shape and distribute timing under real noise and delays.

The PLL is a beautifully complex and common circuit in ICs that reward high-level analog-design intuition. That is, begin at the architecture level, make sure your design is feasible, and work your way down to transistor level implementation.

At its core, phase locked loops generate clocks from a reference source. This sounds simple, but actually finds use in a wide variety of applications:

• Frequency Synthesis: Generate a range of frequency multiples for sampling, DSP, SerDes, RF LO, etc…

• Clock Recovery: Recover data from a bit stream of asynchronous data without a clock reference

• RF Channel Selection: Select channels across specific frequency channels in transceivers

The question is, why do you need a PLL anyways? Why can’t you just use a reference clock?

Well there are a number of reasons:

• Generating internal clocks from a reference- different parts of a system need different internal clock frequencies at different multiples.

• Frequency tuning - The PLL frequency can be tuned by controlling parameters

• Shaping jitter / phase noise - A PLL “reshapes” noise from a reference source and can be optimized in a way to minimize it. Inside the loop bandwidth, the reference/PFD-path noise tends to dominate; outside that bandwidth, the VCO noise dominates.

• Clock skew compensation - In systems with long signal distribution, A PLL can adjust for signal delays across the chip by adjusting its “phase” to be in sync with the original clock.

I want to give a survey level overview of the major design considerations of a PLL at different abstraction levels, from system level, to transistor level, to noise analysis. More detailed information can be found in the book “Design of CMOS Phase-Locked Loops” by B. Razavi [2].

High level design principles

The idea with system architecture is to detect problems at the highest possible level of abstraction.

Typically, at this stage, global stability is owned by the architecture. The architect models the transfer function of the PLL architecture through gain, integrator, and filter blocks.

At this stage there are several things modelled:

• Speed - how high are the frequencies needed?

• Loop bandwidth and phase margin - how fast does the loop need to be to meet the lock time / overshoot requirements?

• Tuning Range - What range of frequencies need to be supported? What VCO gain is required to support this frequency range?

• Capture range - What range can the PLL pull-in from unlocked?

• Lock/hold range - What is the frequency range over which the PLL stays locked once locked?

• Sensitivity - What are the worst case corners with respect to global / random variations? What are critical mismatch sensitivities?

• Noise - Where are the major contributors of noise to the output jitter / phase noise?

• Spurs - where are reference spurs and fractional spurs?

These issues are investigated in a high level modelling language like VerilogAMS or Simulink.

More local stability issues can be left to transistor level designers like op amp phase/gain margin and gain-bandwidth tradeoffs.

The worst thing you want is to jump to transistor level design with a process and find you can’t implement the frequency or obtain the desired phase noise with the given process!

An Intuitive Look into Type I and Type II Phase Locked loops

The basic idea behind a PLL is that it is a closed-loop system designed to synchronize the output clock to the input reference, whether that be a:

• Crystal oscillator

• External system clock

• Data stream

It does this with the following blocks:

• Phase-Frequency detector: Responds to both phase and frequency differences and generates a stream of pulses.

  • Note that “Phase detector” is used in type I PLLs like in the XOR gate, where the frequencies are already close.

• Loop Filter: Filters the input to provide a control voltage Vctrl into the voltage controlled oscillator

• Voltage Controlled Oscillator: Produces an output frequency as a proportion of the input control voltage with a loop gain:

  

• Divide-by-N Counter: Divides the output frequency down by integers of N, allowing the output frequency to be a multiple of the input frequency and the resulting divided clock to be compared against the reference.

The PLL “captures” the frequency from an initial value and adjusts itself until the reference frequency tracks the input frequency. Below is an example of a PLL locking to 7.5MHz in 80us from startup:

Ideally, when a PLL is in “lock”, the average frequency matches and the phase error settles to a small constant (nearly 0). The voltage on the VCO is a DC value with periodic “ripples” to micro adjust the frequency.

The dynamics of a PLL are similar to damped oscillator systems, with a few different “types” of PLLs:

Type 1 PLL: XOR and RC LPF

In a simple implementation, one can simply implement the above with an XOR and and RC Low pass filter.

It is type I because it only has 1 integrator:

• The VCO

So it has one pole at the origin, and another pole at the RC corner frequency.

However, there are two drawbacks:

• Poor lock acquisition - A type 1 PLL often needs the VCO to be initialized close to the target, or else acquisition can be slow or fail without an initialization mechanism

• Non-zero static phase error in lock - In lock, a Type I loop typically requires a constant phase offset to sustain the DC control voltage.

Type 2 PLL: Charge Pump

The Charge Pump is a common block used that sources / sinks current into the filter.

Charge Pump PLLs are considered Type II because this system has 2 integrators:

• The VCO

• The Charge pump current pulses + loop filter capacitor that integrates current to voltage

There are two poles at the origin, and a zero formed by the R.

C2 is added as a high frequency bypass to reduce voltage ripples across Vctrl. C2 is usually smaller, about 1/10 or 2/10 of C1.

Type II integrators can drive steady state error to 0 even with a constant frequency offset, allowing for better tracking and acquisition.

Bode Plots Comparison for Type I and II PLLs

The open loops gains are different for type I and II. Notice how in the type II case, the R introduces a zero that adds phase lead (+90 deg), improving phase margin and stability.

The Transfer Function of the type II PLL

To design a PLL, one must first understand its dynamics through a transfer function. Note that C2 is neglected from this analysis because its value is small compared to C1.

In this derivation, the loop variable is phase, and gains are expressed in the usual PLL units (PFD/CP gain and VCO gain).

The open loop transfer function is given by:

To obtain a closed loop transfer function from an open loop form H(s) and Feedback component G(s):

Substituting H(s) into the above:

There’s a lot of terms here, but the key thing is that this is a second order transfer function of the form:

With damping factor:

And natural frequency:

If you recall second order transfer functions, the output “response” can be over or underdamped.

Now that we’ve seen the blocks and built some intuition, we can add additional layers of understanding on top of it. After the paywall we’ll define the common blocks that are used, define where noise and jitter show up, and give a high-level introduction to fractional-N PLLs.

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In the mean time, check out my other posts to see the systems that PLLs commonly interface with, as well as how to learn more efficiently:

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Editors note (6/1/26) - Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. I added links to additional posts I wrote that interface with Bandgaps after I originally wrote this one. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

However, I’ll leave this post free to get a flavor for the type of depth I go into.

A bandgap reference generates a stable voltage with low sensitivity to temperature, supply, and process (often with trimming).

Most IC datasheets specify that the IC will work within a specific temperature range (such as -55 ̊ C to 125 ̊ C). Variations in temperature can shift bias points and thresholds enough to break specs without a stable reference and proper matching.

Bandgap references are found in virtually all analog circuits as stable references for high-precision analog functions, such as ADCs, DACs, and comparators. They are also used to bias current mirrors for setting bias points so that the resulting circuit is robust to PVT variations. Because of their ubiquity, they tend to be reused and modified depending on the fab process and the level of precision required.

Bandgaps look simple, but are a delicate balance of a few fundamental analog principles, including:

• Matching: resistor ratios, BJT area ratios, amplifier offsets

• Feedback: Forcing ΔV_BE and setting I_PTAT robustly

• Temperature variation: How BJT and resistor characteristics vary over temperature, sometimes nonlinearly

• Trim & Calibration: Output accuracy, temp trim, and curvature correction

Below is a self-biased bandgap design example I built that illustrates these principles. I also have a fun side story at the end about how a group of young designers “competed” on who can make the best bandgap.

Circuit Analysis

Consider the Brokaw Bandgap reference in Fig. 1. The reference voltage is the output of the op amp. This circuit sums a PTAT voltage and a CTAT voltage:

• A PTAT voltage (Proportional to absolute temperature) means that the voltage increases with increasing temperature.

  • The PTAT voltage is generated by the BJT base - emitter voltage difference ΔV_BE = Vt*ln(n) by forcing two BJTs to operate at different current densities (often via an emitter-area ratio n). This voltage appears across R3 in the above example.

• A CTAT voltage (Complementary to absolute temperature) means that the voltage decreases with increasing temperature.

  • The CTAT voltage is generated across the base-emitter of the BJT which behaves like a diode. The reason behind this is related to the fact that the bandgap energy of silicon decreases with increasing temperature.

Additionally, the op-amp sets the PTAT current by driving the loop so its input nodes match (in the ideal case).

When both PTAT and CTAT voltages are summed with the right scaling, the first-order temperature dependence largely cancels, leaving a much flatter reference over temperature.

Derivation of Output Voltage

The derivation of the output voltage is as follows. Starting from KVL:

The current through the circuit flows through R2, where the voltage across it is the difference of the base-emitter voltages of Q and Q1:

Is is the saturation current of the diode. Substituting all of the terms:

The op amp uses negative feedback to ensure that I1=I2, so both terms can be cancelled. However, Is1 and Is2 are proportional to the cross sectional area of the BJT. Therefore,

where n is the number of BJTs in parallel for Q₀. The output voltage is given by:

The output voltage is the sum of a PTAT voltage (Vt) times a gain term and a CTAT voltage Vbe1. However, the temperature variations are not the same. The temperature variations of each term are:

The values in the term R3/R2*log(n) are selected such that the dV/dt of both terms cancel each other:

• n = 8 is common because 8 unit devices plus 1 unit device can be arranged symmetrically (e.g., a 3×3 array) to improve matching.

• The resistor ratio R3/R2 is selected to be equal to 5.5.

Using a bias current of 55 uA and Is1 = 6.734 fA from the SPICE model, and substituting all of these values in the equation above:

• Vbe1 = .59V.

• V_ref at 27 °C = 1.18V.

Circuit Schematic and Simulation Results

The circuit consists of the bandgap core which generates the PTAT and CTAT voltages. Both collector voltages are fed into an op amp which uses a PMOS differential pair as the first stage. This is done to avoid the VMIN problem an NMOS based op amp would experience since the common mode input voltage is approximately 1.18V.

The output of the first stage is fed into a second stage where the output is referenced to the VDD rail to control the PMOS current sources. The op amp is biased with a PMOS based cascode current mirror of 20uA. All of the DC voltages and currents are shown at T = 27 °C.

The simulation results of the bandgap reference are shown below.

Output voltage across temperature. The graph above shows the DC value of Vref as temperature swept from -55 °C to 125°C in 1°C increments. Ideally, the voltage should be flat across temperature, but the simulation shows the voltage follows a parabolic shape. The maximum voltage is 1.1885V which occurs at approximately 30 °C. The voltage drops for lower and higher temperature, where the minimum voltage is approximately 1.1869V. When the voltage is confined to this range, the maximum voltage difference is 1.6 mV, which is a variation of 0.14% over temp.

Line Regulation. This simulation sweeps the value of the voltage supply for three different temperatures: -55 °C (left curve), 27°C (middle curve), and 125 °C (right curve). The reference voltage stabilizes when the power supply has reached a certain threshold. This threshold is different for all three temperatures and is shown in Table 1. Once the power supply voltage has reached its threshold, the reference voltage is fairly stable.

Power supply rejection ratio, or PSRR. The PSRR is the ability for the circuit to reject noise from the power supply. It is defined as:

To perform this simulation, an AC signal of 1 mV was places in series with the power supply voltage. An AC sweep was performed for three temperature values from 100Hz to 100MHz and the magnitude of the output voltage was observed. The above formula was then applied to obtain the plots shown above, with results shown in table 1.

Mismatch in R10 Resistor. The resistance was swept parametrically from 5kΩ and 6kΩ in 100Ω increments and the output voltage is plotted. This simulation shows that for low resistor values, the CTAT voltage of the BJT dominates the characteristic, and the curve drops over temperature. When R10 is high, the PTAT voltage dominates, and the reference curves increase over temperature.

The following chart summarizes the simulation results.

Additional Features

There are additional features that bandgaps need:

Trim Range. The degree to how precise a bandgap has to be depends on the precision required across PVT. Monte carlo simulations are run to determine the untrimmed range over which the output voltage can vary, and trim features are added in appropriate places to ensure the output voltage can be turned to within spec across the temperature range.

Curvature Correction. Parts that operate in wide temperature ranges with tight specs can require additional “curvature correction” to improve the error across temperature. First order cancellation like resistor-only tuning can give residual curvature because parameters can have nonlinearities across temperature (such as BJTs) that affect the output.

Startup Circuitry. Because the core is self-biased, it has a zero-current equilibrium point, so startup circuitry is required to guarantee the intended operating point.

Story time: A Friendly Bandgap Competition

At an Analog Design internship, I once saw a group of young engineers have a friendly completion against each over who can design a bandgap with the highest accuracy across temperature. Work was to be done after 2-3pm on Friday so as to not interfere with day to day work.

Most of the “tricks” they experimented with involved:

• curvature correction techniques, like how to bias a transistor to turn on as a specific temperature, and where to place in the circuit

• NPN / PNP topologies

• value ratios (n, resistors)

• what current mirror to use (cascode, wide swing, source degenerated, wilson)

• what amplifier topology (NMOS, PMOS, gain stages, active loads) maximize gain and minimize offset

Each participant presented their results weekly and learned insights from each other to improve their day job, since analog is an art after all.

Conclusion

I feel like designing bandgaps are a really good introduction to analog circuit design because designing them develops a lot of the fundamentals used in more complex analog circuits.

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If you’re curious about how bandgap references are used in higher level systems, check out my other posts here:

References

[1] Timm, S. Wickmann, A., “A Trimmable Precision Bandgap Reference on 180nm CMOS”, Semiconductor Conference Dresden-Grenoble (ISCDG), 2013 International, 26-27 Dept. 2013, http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=6656292

[2] Hugo. “Bandgap voltage Reference” [Online]. Available: http://www.onmyphd.com/?p=bandgap.reference

[3] P. Miller and D. Moore. (2005). “Precision voltage references” [Online] . Available: http://www.ti.com/lit/an/slyt183/slyt183.pdf\

[4] A. Paul Brokaw. (2011). “How to make a bandgap reference in one easy lesson” [Online]. Available: https://www.idt.com/document/whp/how-make-bandgap-voltage-reference-one-easy-lesson-paul-brokaw

I think of analog design as one of the more "artful" branches of electrical engineering. It requires deep intuition, careful tuning, and a sensitivity to both device-level physics and system-level performance.

This post will be a survey-level overview of each of the major abstraction levels from system architecture to transistor-level design. I want to provide a “top down” perspective of what happens at each stage of the process, so you understand how your work fits into the bigger picture.

Note: My background is deeper on the design side than dedicated system architecture and verification. I’m aiming to describe both flows at a high level and keep details intentionally light.

System architecture and modeling

Product definition translates customer/market needs into requirements (performance targets, interfaces, constraints, operating conditions) that guide architecture.

Usually, the modeling begins with an “ideal” model of a high level system. Then, levels of fidelity are added to analysis the impact on the overall system performance. This enables architectures to analyze the feasibility of a proposed topology and catch system-level sensitivities - including noise, bandwidth, and mismatch — before specifications are handed off to individual blocks.

This level of fidelity include fab-specific models:

• Switching models of transistors to model anticipated loss

• Non-ideal components

System-level modeling tools shine at this level. These include MATLAB/Simulink, Simscape, Verilog-AMS, and SystemVerilog. They allow you to:

• Co-simulate analog and digital behaviors

• Evaluate loop stability (e.g., PLLs, regulators)

• Explore tradeoffs before committing to transistor-level design

Examples of such systems include:

• 3L Power Converter

• Serdes Transmitter

• RFIC superheterodyne Transmitter

In summary, you want to make sure any potential issues / spec defining features are verified at the highest abstraction level with as much fidelity as possible, before passing work down as specifications and requirements to low level blocks.

This process is done while specifying blocks at a high level, such as high speed SerDes:

Design + verification: two mindsets

After system architecture, the work gets split down into two “tracks” that coordinate tightly with each other:

Block level design: implement transistors in the given process through schematic entry and layout, and make sure they are robust against PVT and aging.

Verification: try to break assumptions and validate correctness across modes/corners/interactions (often using behavioral models + mixed-level sims + regressions)

The boundary between design and verification can be a little fuzzy at times based on the complexity of the chip. Sometimes designers end up doing verification alongside design. Other items there is a dedicated verification team that adopt formal verification practices from digital like UVM.

But can’t you just simulate transistors all the time? You can, but its computationally expensive. I want to stress three points:

• Transistor-level sims can be slow and unpredictable in runtime, which stretches the feedback loop.

• EDA licenses are limited and expensive

• Designer time is valuable and wants to focus on high level issues

In short, it is advantageous to use behavioral models if you can and simulate with Spectre when reasonable.

Behavioral modeling / co-simulation

Verification is becoming increasing important in the analog domain as well as complexity grows and simulations take longer to simulate.

Early on, teams build behavioral models of blocks to enable fast system simulation; later, those models get refined or swapped with transistor implementations as blocks mature.

Each transistor level block is “verified” by co-simulating it with behavioral models of the blocks it is supposed to interact with. The “config” view in cadence is used to swap out behavioral and transistor level views to get a feel for how blocks interact with each other. This way, one can ensure that the system behavior remains the same as transistors are slowly added.

Some teams borrow structured digital verification practices (UVM-style regressions, assertions/checkers, coverage mindset), adapted to mixed-signal.

How much behavioral modelling is needed depends on the complexity of the system:

• Behavioral modelling is not always required for standalone analog blocks (like an LDO for a processor)

• Behavioral modelling becomes much more important as more complexity is added onto chips, integration becomes tighter, and risk goes up of bugs.

There is an excellent paper to learn more about the design vs verification mindset called “Verification Mind Games: How to think like a verifier” [1] that I will direct you to learn more about.

It’s like the saying goes, “Trust, but verify”.

Transistor-level block design

I like to think about transistor level design as a multidimensional optimization problem. There are a dozen different paths you can go down to implement a specification, but you only have so much time.

Once block level requirements are defined:

• Start with a base circuit topology or existing IP that fits the function, speed, and power envelope

• Identify alternatives to topology - are there others that offer more benefits or improvements. You might look into research to identify promising ideas, or try your own.

• Optimize device sizes (W/L, resistor / capacitor values) to make your design robust

One key challenge is sizing components. Digital often pushes toward minimum dimensions for speed/area, while analog frequently uses longer L in critical devices to improve matching, gain, and noise. Here are some guidelines I’ve heard:

• Often 2-10X minimum L for current mirrors. Larger L values improve matching

• Size W based on current handling capabilities and gm for amplifiers

• Larger devices (W*L) sizes generally reduce Flicker 1/f noise

• Make capacitors large enough to reduce fringing effects

Scaling parameters can be used in schematic to keep device sizes ratios of each other and avoid any unnecessarily large devices. Sometimes, performance specs can be limited by devices sizes, especially on chip capacitors, so any devices need to be added externally.

At this level you’re dealing with “second order” effects from physics and variability, such as:

• Noise (thermal, shot, flicker)

• Body effect

• Short Channel Effects

• Matching

• Charge Injection

• Parasitic BJTs

In addition, you need to ensure that your design is robust against process variation, aging, and non idealities. This includes:

• Simulation across corners (PVT), layout parasitics, and aging (e.g., High Temperature Operating Life or HTOL) to ensure robustness

• Monte Carlo to evaluate mismatch/statistical variation.

• A Parasitic Extraction (PEX) at the end to verify overall circuit functionality

There are two key concepts analog people need to know: trimming, and test modes:

• Trimming. Trimming is when a value of a voltage in a circuit need to be adjusted due to process variation.

  • Monte Carlo simulations are used to evaluate the expected trim range of a parameter

  • Trimming is typically implemented with digitally selectable elements (e.g., resistor strings, current/Cap arrays, DAC trims), programmed via fuses/OTP/register settings depending on product.

  • The level of precision depends on how precise the value need to be to drive downstream blocks or for customer specs.

  • Global references (bandgaps, oscillators/PLLs) are common trim targets because many downstream biases and timings depend on them.

• Test Modes. Much analog functionality is hidden from the customer through “test modes”. Test modes can be thought of as “internal debugging tools” to obtain insight into what a circuit is doing at specific points. These add extra “probes” to analyze the actual circuit behavior and allows experiments to be run and observe. These are also “knobs” that you can turn to run various experiments. Typically, test mode values are written in registers that are hidden alongside the trim registers.

  Adding test modes help “future proof” your design against bugs by providing more probes and knobs to turn. If there are any weird bugs, especially in new IP, you have additional insight to look at to analyze behavior and compare against simulation expectation.

Block level design is where designer intuition matters most — knowing what to tweak and when, how to recognize subtle failures, and when to trust the simulation (or not).

A map of common analog building blocks

Here are some “Textbook” circuit topologies and IP blocks that commonly appear in analog design from the low level biasing to more system oriented.

Biasing

• Wide-swing cascode current mirrors

• Bandgap references

• Current Reference

• Low Drop Out Regulator

Switches

• Transmission Gate

Clocking

• Ring Oscillators

• Phase Locked loops

High speed

• Fundamental two stage op amp

• Folded cascode OTAs

• High speed comparators

• Gm-c Filters

High Precision:

• Switched-capacitor circuits

Power amplification

• Dickson Charge pumps

• Gate Drivers with series inverters

ADC / DAC:

• Charge Redistribution SAR ADC

• Delta Sigma ADC

Support:

• Common Mode feedback

• Level shifters

Once blocks are defined, they can be stitched together to construct more complicated systems.

I wrote foundational primers on several of these blocks here:

Conclusion

Analog Design is such a vast, field that many designers genuinely enjoy working in, but also challenging to understand without a mental model in your head to reference into the types of activities going on around it.

In summary:

• Start from the highest abstraction level

• Add fidelity as you can until you need it to save simulation speed and root out problems

• As more complexity is added, simulate transistor level performance using fab models against fab corners

• Simulate PEX near the end

  Silicon Co-Design is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber.

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I have several block level primers above, as well as an architectural breakdown of a high speed SerDes:

References

[1] J. Montesano and M. Litterick, “Verification Mind Games: How to think like a verifier,” paper presented at DVCon (United States), Mar. 4, 2014. [Online]. Available: https://cdn.prod.website-files.com/63f4bb21bd5303fe472ad00e/649596eab21cab357fc424b7_verification_mind_games_final.pdf

Editors Note: 6/23/26: Throughout this post, I added several links to my deep dive posts I wrote after I originally wrote this post give you a broad perspective into the way I applied this methodology to breaking down complexity in those posts, including a fully free SAR ADC post.

There is a paywall in the last two sections where I describe the process of breaking down architecture level tradeoffs and building up intuition of more complex blocks from simpler ones with a folded cascode OTA as an example.

Most frustration in learning hard things comes from starting at the wrong zoom level.

I tried learning complicated things in analog design too early, like folded-cascode OTAs and PLLs in undergrad. I would get stuck fast — not because I wasn’t capable, but because I was being pulled into details before I had a mental frame to hang them on.

The turning point for me was realizing:

Complex topics don’t become easier when you memorize more details or view more lecture videos.
They become easier when you build better foundations and organize the details logically.

Here are the four moves I use to understand complex fields:

• Pick one foundation source (one teacher)

• Bottom-up summary (principle of operation)

• 🔒Top-down map (hierarchical outline of concepts)

• 🔒Relate advanced concepts from simpler ones (Folded Cascode OTA)

I’m going to use a few real analog design technical examples to make the method visible (because analog can get wonderfully complex).

Choose your foundation learning sources carefully

When learning a complex field, start with one “foundation source” that’s known for clarity, then translate it into your own mental model.

• In analog design, that might be Razavis book and lecture videos.

• In machine learning, that might be Andrew Ng’s Coursera courses.

The specific source matters less than the principle: pick one clear teacher, build your base, and then other authors start becoming more clear because you finally share the same “background assumptions.”

Once you’ve identified your foundation sources, the next step is straightforward: work through the material — read the chapters or take the course.

Bottom up Summary (Principle of Operation)

Read dense sections slowly and translate the author’s explanation into a “principle of operation” summary in your own words.

Example: Understanding Switching Behavior of a single transistor in Power Electronics

This method matters especially in power electronics, because switching waveforms can look intimidating at first glance.

A switching cycle has a lot happening in a short time:

• different devices turning on/off,

• different current paths,

• different energy transfers

all across multiple time intervals. If you try to absorb the full diagram in one gulp, it becomes confusing. Take the following switching diagram for a gate driver driving a single transistor:

So here’s what I do:

• I read the author’s explanation of how the circuit works. Typically this is very dense and has a lot of equations for rigor.

• As I’m reading, I break down the switching diagram into three intervals.

• In each time interval I’m writing a one line summary of what each voltage / current is doing.

  • T1: the “precharge phase” :

    • V_gs increases to V_th

  • T2: the “miller phase”:

    • V_gs increases slowly as V_ds transitions from V_bat to 0

  • T3: end of “miller phase” :

    • I_load reaches its peak

    • V_gs continues charging up to its peak value

• I bold important concepts to make them easier on the eye to reference later (like the “Miller plateau”.)

Here are my personal notes where I write the principle of operation in my own words as I went through this section the first time:

You might not explain the principle of operation the same way as me, but the point is that:

You summarize the material in a way you understand.

I have a post on the fundamentals of buck converters where I used this method to break down the principle of operations:

Top down - Hierarchical Breakdown of Concepts

I break down concepts broken down in a bullet format from high level concepts to low level ones that helps quickly “cue” the concept and retrieve the information I summarized earlier. This can apply to both architecture level and complex analog blocks

Here I will illustrate this with an ADC.

Example: ADC Architectures and Tradeoffs

I started reading the basics of ADCs on “Analog Integrated Circuit Design” and create a top level hierarchy of “textbook” topologies for various applications:

• ADCs

  • Low - medium speed, high accuracy

    • Integrating

    • Oversampling / ΔΣ

  • Medium speed, medium accuracy

    • SAR

    • Algorithmic

  • High speed, low to medium accuracy

    • Flash

    • Two step

    • Interpolating

    • Folding

    • Pipelined

    • Time-interleaved

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One popular ADC is the SAR ADC. Check out the important design considerations in this post:

Under each of these topologies, I expand into more detailed sub-architectures, including:

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