As data speeds climb from 112Gbps to 224Gbps and 448Gbps, data starting running into physics constraints and transceivers become more complex to compensate for these effects.

In this post I’ll be doing a system architecture breakdown of a modern DSP-based transceiver. I’ll explain the underlying physics constraints and the major blocks data passes through. Then, I’ll do a deep dive into the high-speed building blocks (shown in yellow) on the TX and RX side. I’ll be covering the following:

• The real problem: increasing data throughput under physical limits

• System Datapath overview

• TX Architecture:

  • Serializer / Mux tree

  • DAC - 6-7 Bit current steering DAC

• RX Side - Time-Interleaved ADC

• 🔒Clocking Architecture

  • 🔒Clock Recovery: Bang Bang Phase Detector

  • 🔒Clock Generation: LC-VCO Based PLL

  • 🔒Multi-phase clock generation: The phase Interpolator

  • 🔒Clock Distribution: Repeater, transmission line, and resonator-based

Most of the figures in these slides are from the ISSCC tutorials as well as the papers in the references.

The real problem: increasing data throughput under physical limits

As data rates climb, we need to ask ourselves: what fundamentally constraints the data speed from first principles?

Data speed is now limited by physics and device parameters on the chip, which include, but not limited to, the following:

• Channel Loss: Loss scales with signal frequency, and high frequency attenuation rounds out the sharp edges of digital signals

• High impedance nodes in analog circuits: Active loads have a high input resistance, which is good for gain, but also creates dominant poles that lower overall BW.

• On-Chip Capacitance: Bigger transistors have bigger C that can affect rise/fall times of signals

• Noise / Jitter: The randomness in clock / data edges affect how fast those signals can be relative to the clock period. This impacts reliability of high speed digital circuits and time-interleaved switches

What tricks do designers have to increase speed? I contend there are two major paradigm shifts:

• Current steering circuits: These circuits steer constant currents through switches to a resistive load. The main advance is that it minimizes charging/discharging time of parasitic capacitors. However, current steering circuits tend to consume more power than equivalent charged-based topologies.

• Time interleaving: Instead of making a single component faster, place many in parallel and distribute data through “ranks” of S/H and T/H switches. Time interleaving introduces added complexity in clocks to coordinate parallel operations

System Datapath overview

Next lets look at the major blocks in the datapath.

The function of a transceiver is quite simple: transmit a large amount of data from the TX and RX with minimal errors across a medium as fast as possible.

For short reach, low speed operation, the architecture relied mostly on analog blocks. However, due to recent data demands, one of the big paradigm shifts is a move to digital for the processing. Digital is great at performing parallel processing of data at a moderate clock (1-10’s GHz) frequency.

However, when it comes to data transmission, edge density becomes the constraint. You can only pack so much circuitry to drive the parallel channels on the edge of a chip and copper cables in the system.

As a result, data transmission favors serialized data at a high speed to pack as much data density as possible and transmit on a single cable.

These constraints influence the architecture of modern wireline transceivers.

On the TX Side, the main high speed blocks include:

• Forward Error Encoding (FEC) - Encodes the data with parity bits that correct for channel error at the RX side

• Feed Forward Equalization (FFE) - Pre-distorts the signal using a FIR filter to compensate for channel losses

• Serializer - Serializes the digital data from multiple channels and raises the effective output rate. 112 Gb/s PAM4 corresponds to a 56 GBd symbol rate, though practical serializers often use half-rate or quarter-rate architectures that are time-interleaved

• High-speed DAC - turns digital symbols into an analog waveform

• Driver - amplitudes the signal before it is transmitted on the channel

In the Channel:

• Matching network - matches the TX and RX to the characteristic impedance to avoid reflections and transmission line effects

• Channel - attenuates and distorts the transmitted signal

In the RX:

• Receiver front-end - conditions the signal by amplifying it (variable gain amplifier) and providing equalization (CTLE)

• TI-ADC - converts the analog value to digital values

• Deserializer - converts the digitized data from the transmission rate to the digital frequency

• DSP - processes and recovers data

As a result of the added digital complexity, high speed and parallel processing blocks require a robust clock architecture to synchronize the data properly.

In the following sections, we’ll step through each of the high speed blocks, with the principle of operation, the key impairments, and how they affect the system level.

TX Architecture

Serializer / Mux tree

The mux tree is used for serializing / deserializing data. Here, stages of 2-1 muxes are arranged in ranks. This ensure each interconnect between muxes aren’t heavily loaded that can slow down operation.

The final rank operates with the highest-rate clock, while earlier ranks use divided versions of that clock so that each stage runs at a rate compatible with its local data rate.

A common high-speed mux cell is the current steering mux cell. This cell uses two differential pairs for each of the inputs. To select each input, the SEL signal, synchronized to the CLK, steers the current between the two input branches.

Impairments

• Kickback noise from clock feedthrough. Clock feedthrough and switching transients can disturb internal common-mode nodes and degrade timing margin, especially in the final high-speed stages.

• Skew between SEL and clk.

• Skew between stages in the MUX tree. The accumulated clock delay associated with the driver and the mux itself can cause ranks to fail to clock the data fast enough.

DAC - 6-7 Bit current steering DAC

The high speed DAC commonly employs a segmented current steering architecture. This architecture uses scaled current sources representing the “weight” of the binary bits. The steered currents are summed and converted to an output voltage across a load impedance.

The current steering cell consist of two main branches and a selector with a flip flop and driver. This current source is generated from the bottom two transistors. The driver cell “steers” this current between two branches: the left branch to enable the bit and right branch to disable it. The switch control is retimed so current steering occurs with precise timing at the symbol rate.

Current continuity is often preferred for high speed because it minimizes voltage swings from constantly charging / discharging capacitive nodes. However, it also consumes static power even when the bit is disabled.

This current cell is then scaled to a segmented architecture, which uses both unary and binary DACs. Unary (or thermometer code) uses unit-sized current sources arrayed in a 2x2 grid in layout to achieve better matching of current sources.

In many wireline transmitters, DAC resolution is kept modest, often around 6–7 bits, because channel loss, jitter, and front-end noise dominate before very fine quantization does.

Impairments

There are several impairments that cause both timing and amplitude errors:

• Time delay

• Voltage glitches

• Clock Skew

• Finite Input impedance

• EMI at all sources

  

These impairments introduce timing and amplitude error at the system level. They translates to jitter in the x domain and noise in the y dimension. These effects directly affect the size of the “eye” at the RX side, so it is important to account for these and spec these appropriately.

RX Side - Time-Interleaved ADC

A common modern RX approach uses time-interleaved asynchronous SAR ADCs operating in a self-clocked manner.

In normal asynchronous SARs, it takes N clock cycles to complete an N bit conversion. In asynchronous circuits, self-clocking allows the completion of one comparison to automatically trigger the next.

Self-clocking removes the need for a very high external clock, but it makes the conversion timing dependent on timing delays and handshake robustness.

Asynchronous SARs are commonly used due to low comparator count, simple digital logic, and capacitive DACs for energy efficient operation at typical 6-7 bit resolution.

These SAR ADCs are time interleaved. The high speed data is “fanned out” to each of the sub-ADCs in order for their analog values to be digitalized. This is accomplished through a two-rank NxM interleaving scheme. This architecture performs sampling in two ranks:

• Rank 1 - Track and hold. The first rank tracks and holds the signal. The performance of these switches are critical as they sample the full BW signal.

• Rank 2 - Sample and hold buffer. These buffer the T/H signals to drive the parallel ADCs.

In modern PAM-4 112Gbps, the interleave factors range from 36-128 sub-ADCs depending on the layout area, with 64 being common. [1]

Impairments: There are several impairments:

• Skew and Jitter of clock

• Mismatches between sub-ADCs

These impairments translate timing mismatches into sampled voltage errors, often in a signal-dependent way, and can create both noise-like degradation and spurious tones.

Clocking Architecture

Perhaps the most important part of a high speed chip is the one everyone takes for granted: The clock.

The clock distribution becomes an increasingly important constraint as dimensions and speeds have scaled down. There are several challenges the clock faces:

• The clock needs to be recovered from the asynchronous RX data to ensure that the clock is in “sync” with the data to clock it appropriately

• The VCO needs to generate a reference clock with low jitter

• The time-interleaved blocks need some form of multi-phase clock to synchronize operations across parallel processing elements cleanly

• The parallel clock distribution needs minimal skew to minimize mismatches

After the pay wall I’ll describe the clocking architecture in more detail.

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If you want to get a flavor for the adjacent domains involved, I have several other posts to check out as well:

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This post covers the following topics:

• The Mixed-Signal Interface: Core Building Blocks

• The Binary Search Algorithm

• Charge Redistribution DAC

• Important Specifications

• Important Nonidealities

• Calibration

ADCs are the toll booth amongst multiple “worlds” on the chip. When a signal gets converted from one world to another, a “tax” is paid in the form of power consumption, latency, or accuracy.

Successive Approximation Register ADCs (SAR ADCs) are widely used due to their amazing versatility. They can be optimized for speed, resolution, or both due to the ability to scale the architecture in the analog and/or digital domains.

SAR ADCs have seen great use especially as process nodes allows complexity to be abstracted in digital. They are used in a variety of applications:

• RF / Wireline transceivers

• Sensing (Touch, Biomedical)

• Analog Compute-in-Memory

In a real system, such as a modern wireline transceiver, ADCs often interact with other blocks such as PLLs to generate the clocks, LDOs to power the circuit, bandgaps to generate the references, and DSP to do digital post processing. Additionally, SAR ADC can be time interleaved to increase data throughput.

The Mixed-Signal Interface: Core Building Blocks

SAR ADCs use a DAC in a feedback loop that compares the input against digital code. The digital codes are adjusted until the error is minimized in the comparator.

A SAR ADC comprises of the following building blocks:

Sample and Hold. This circuit samples the signal at a sampling frequency fs and holds it in place for conversion

Comparator. A comparator compares the input reference to the DAC output and tells the SAR logic whether to increase or decrease the voltage

SAR Logic. A digital block that implements a “binary search algorithm” by cycling through digital bits in response to the voltage error

DAC. This block converts the digital code into an analog value to be compared against the input reference

SAR ADCs have the following output transfer function that resembles a “stairstep”:

This is the ideal behavior, but SARs ADCs are very sensitive to matching, noise, and non-ideal components that cause the output to deviate from this ideal stairstep. These effects are especially pronounced in the DAC. Good layout techniques as well as calibration can be used to compensate for the errors. More on that later.

The Binary Search Algorithm

SAR ADCs use the “binary search algorithm” in order to figure out the right digital code that minimizes the error between the voltage input and the DAC output.

Binary search is an algorithm that is widely used in SW for storing values in a “tree” structure with left nodes for lower values and right nodes for higher values. In the context of SAR ADCs, the basic idea is that:

• If your DAC voltage is higher than the reference, adjust the digital bits to make Vout lower

• If your DAC voltage is lower than the reference, adjust the digital bits to make Vout higher

This process takes place from coarse resolution to fine resolution. That is, you make your biggest voltage changes first, then you make smaller voltage changes as you narrow in on the closest digital value.

To complete an N bit conversion, N clock cycles are usually required. For this reason, there is a fundamental tradeoff between speed and resolution since it will take longer for the circuit to converge on a higher resolution value.

Charge Redistribution DAC

This SAR logic feeds into a DAC, which is most commonly implemented as a charge redistribution DAC. Shown is a fundamental architecture that explains the behavior, and served as the foundation of understanding more modern implementations. [1]

Here, the capacitors are binary weighted. There are three phases of operation:

Sampling phase: Sample the input onto the capacitor array

Hold Mode: Disconnect the input and establish the initial comparator condition

Bit Cycling: Successively switch capacitor elements between reference levels to test each bit decision

In some implementations, the capacitor array is switched between a + and - Vref voltage. In other implementations, Vin is directly connected to the top plate of the capacitor array that is switched off during conversion

One major source of error in binary DACs is capacitor mismatch, which can get bad as capacitor sizes get exponentially larger with increasing bits with binary code. The mismatch caused by capacitor ratio errors can cause errors in your codes that makes your effective resolution much lower than what your DAC architecture supports.

To get around this, a technique called “segmentation” is used.

Segmented DAC

Segmented DACs allows ADCs to be “customized” by blending different architecture for the MSBs and LSBs. Segmented DACs split the architecture in two “halves”:

• LSBs are Binary Code: Encode each value through a binary weighted sum of caps

• MSBs are Unary / Thermometer code: Encode the MSBs using unary code which uses unit sized capacitor values. These capacitors tend to be “arrayed” in 2D especially as resolution increases.

Segmenting allows much reasonable component sizes and ratios in the binary side and better matching of unit sized capacitors in the unary side. Typically the unit sized capacitors are implemented as a 2D array on chip that can be switched to any size needed. However, this added area does introduce other sources of error due to trace parasitics that should be accounted for.

Another common implementation is using a resistor ladder for the LSBs:

Charge Redistribution DACs allow for low power as the conversion is being done through finite amounts of charge moved around. There are other DAC architecture such as current-steering that optimize for speed at the cost of the power consumed from continuously flowing currents.

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Important Specifications

There are several specifications to ADCs.

Resolution. Resolution refers to the number of distinct analog level that correspond to the different digital words. A 10 bit resolution corresponds to 2^10 or 1024 distinct analog levels.

Dynamic Range. Dynamic range is the ratio of the full-scale input and the noise floor at a small or no signal input. Both quantities are usually measured separately and the different is taken as the dynamic range

Spurious free dynamic range (SFDR). SFDR measures the difference between the fundamental signal and the largest unwanted single unwanted component. It accounts for the spurs that typically comprise a spectrum.

Speed. Speed is broken down into a few different metrics:

• Conversion time - The time taken for the converter to complete a single measurement - including the acquisition time of the input signal

• Latency - the delay between when an input is sampled and when it is ready

  In some cases, the latency can be larger than the sampling time, especially in pipelined ADCs.

Linearity. Linearity is quantified in a few ways:

• Gain Error. Gain error is the deviation of the slope of the converter output transfer function against the expected slope

• Offset Error. Offset error is the DC shift in the converter transfer function from the expected one

• Integral Nonlinearity error (INL). INL describes the deviation of a practical conversion curve from the ideal function

• Differential Nonlinearity error (DNL). DNL describes the deviation of each step with respect to the ideal LSB size

  

Quantization Noise and Error. Quantization error occurs in ADCs because there will always be a small offset between the digitized analog value and the actual analog value itself. This quantization noise is bounded to +- 1/2 LSB and often modelled as random white noise in the system it is in.

Important Effects

ADCs are highly sensitive to matching and noise, as well as affected by aliasing due to the sampling nature.

Aliasing. Aliasing is a broad signal processing phenomenon and occurs when the input frequency is greater than the Nyquist frequency, which is half of the sampling rate. When this happens, the frequency content above Nyquist folds back into baseband and appears as false lower-frequency content unless filtered before sampling.

Matching. Perhaps the number one culprit of nonlinearity is the variability of components. Mismatch standard deviation generally improves roughly with the inverse square root of device area, depending on the parameter and model.

Glitches. Glitches are caused by a few things:

• small voltage blips due to current switching into parasitic capacitors.

• charge injection effect where the charge needed to turn the channel on/off rushes in and out,

• clock feedthrough

Glitches can be reduced through careful switch timing, bottom-plate sampling, differential design, device sizing, and layout.

Calibration

Mismatch in the DAC often necessitates calibration techniques to correct for linearity. There are two classes of calibration:

• Foreground calibration - Interrupts normal operation by taking ADC out of the signal path

• Background Calibration - Does not interrupt normal operation and may run continuously in the background

In each case, a quantity is injected and the raw output is observed and sent through post processing until the entire chains is linear.

Calibration can utilize reference and auxiliary ADCs/DACs to be able to “measure” the raw Dout and correct for it. Calibration can be done in the analog domain or digital domain by pre-distorting the Din to have it align to the nonlinear characteristic of the ADC.

Calibration is often necessary in high precision ADCs to correct for mismatches. However, calibration introduces additional complexity that must be properly characterized.

Conclusion

As you can see, ADCs require an in depth knowledge of analog design because they are highly sensitive to layout and noise, so designing them requires a high level of precision. Component matching is super important because it directly affects linearity. Understanding of noise sources is very important to know how each noise source affects performance.

ADC design can get especially specialized when designing for spec-defining performance in the market and advanced processes where an in-depth knowledge of ADC architectures, effects, and calibration techniques are needed. ADCs are very highly tuned to the specific application and process they are in.

I barely scratched the surface of important considerations on SAR ADCs with this primer, but I hope it helps you give you a mental framework to go more in depth in ADCs and systems they are in. Please refer to the books in the references for more information.

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Also, I have a few primers on blocks that the ADC interacts with on my Substack for further reading:

References

[1] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques. I,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371–379, Dec. 1975.

[2] T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. Hoboken, NJ, USA: Wiley, 2012.

[3] M. J. M. Pelgrom, Analog-to-Digital Conversion, 4th ed. Cham, Switzerland: Springer, 2022.

This post covers the following topics:

• High level design principles

• An Intuitive Look into Type I and Type II Phase Locked loops

  • Type 1 PLL: XOR and RC LPF

  • Type 2 PLL: Charge Pump

  • Bode Plots Comparison for Type I and II PLLs

• The Transfer Function of the type II PLL

• 🔒Common transistor level implementations of type II PLLs

  • 🔒Phase-Frequency detector

  • 🔒Charge Pump

  • 🔒Voltage Controlled Oscillator

    • 🔒LC Oscillator

    • 🔒Current Starved Ring oscillator

• 🔒Important considerations: Phase Noise and Jitter

• 🔒A high-level look into the Fractional-N Synthesizer

A modern chip is like a finely tuned orchestra. Each member of the orchestra knows their role and what notes to play, but needs to know when to play them. The conductors role is to align musicians to a shared interpretation of tempo.

Imagine if there was no conductor; musicians don’t know when to play, so the orchestra gets out of sync really quickly as each person plays to their own tempo.

This is the role PLLs play in circuits: as the “conductor” that produces a clock to keep blocks synchronized to a common reference. PLLs help shape and distribute timing under real noise and delays.

The PLL is a beautifully complex and common circuit in ICs that reward high-level analog-design intuition. That is, begin at the architecture level, make sure your design is feasible, and work your way down to transistor level implementation.

At its core, phase locked loops generate clocks from a reference source. This sounds simple, but actually finds use in a wide variety of applications:

• Frequency Synthesis: Generate a range of frequency multiples for sampling, DSP, SerDes, RF LO, etc…

• Clock Recovery: Recover data from a bit stream of asynchronous data without a clock reference

• RF Channel Selection: Select channels across specific frequency channels in transceivers

The question is, why do you need a PLL anyways? Why can’t you just use a reference clock?

Well there are a number of reasons:

• Generating internal clocks from a reference- different parts of a system need different internal clock frequencies at different multiples.

• Frequency tuning - The PLL frequency can be tuned by controlling parameters

• Shaping jitter / phase noise - A PLL “reshapes” noise from a reference source and can be optimized in a way to minimize it. Inside the loop bandwidth, the reference/PFD-path noise tends to dominate; outside that bandwidth, the VCO noise dominates.

• Clock skew compensation - In systems with long signal distribution, A PLL can adjust for signal delays across the chip by adjusting its “phase” to be in sync with the original clock.

I want to give a survey level overview of the major design considerations of a PLL at different abstraction levels, from system level, to transistor level, to noise analysis. More detailed information can be found in the book “Design of CMOS Phase-Locked Loops” by B. Razavi [2].

High level design principles

The idea with system architecture is to detect problems at the highest possible level of abstraction.

Typically, at this stage, global stability is owned by the architecture. The architect models the transfer function of the PLL architecture through gain, integrator, and filter blocks.

At this stage there are several things modelled:

• Speed - how high are the frequencies needed?

• Loop bandwidth and phase margin - how fast does the loop need to be to meet the lock time / overshoot requirements?

• Tuning Range - What range of frequencies need to be supported? What VCO gain is required to support this frequency range?

• Capture range - What range can the PLL pull-in from unlocked?

• Lock/hold range - What is the frequency range over which the PLL stays locked once locked?

• Sensitivity - What are the worst case corners with respect to global / random variations? What are critical mismatch sensitivities?

• Noise - Where are the major contributors of noise to the output jitter / phase noise?

• Spurs - where are reference spurs and fractional spurs?

These issues are investigated in a high level modelling language like VerilogAMS or Simulink.

More local stability issues can be left to transistor level designers like op amp phase/gain margin and gain-bandwidth tradeoffs.

The worst thing you want is to jump to transistor level design with a process and find you can’t implement the frequency or obtain the desired phase noise with the given process!

An Intuitive Look into Type I and Type II Phase Locked loops

The basic idea behind a PLL is that it is a closed-loop system designed to synchronize the output clock to the input reference, whether that be a:

• Crystal oscillator

• External system clock

• Data stream

It does this with the following blocks:

• Phase-Frequency detector: Responds to both phase and frequency differences and generates a stream of pulses.

  • Note that “Phase detector” is used in type I PLLs like in the XOR gate, where the frequencies are already close.

• Loop Filter: Filters the input to provide a control voltage Vctrl into the voltage controlled oscillator

• Voltage Controlled Oscillator: Produces an output frequency as a proportion of the input control voltage with a loop gain:

  

• Divide-by-N Counter: Divides the output frequency down by integers of N, allowing the output frequency to be a multiple of the input frequency and the resulting divided clock to be compared against the reference.

The PLL “captures” the frequency from an initial value and adjusts itself until the reference frequency tracks the input frequency. Below is an example of a PLL locking to 7.5MHz in 80us from startup:

Ideally, when a PLL is in “lock”, the average frequency matches and the phase error settles to a small constant (nearly 0). The voltage on the VCO is a DC value with periodic “ripples” to micro adjust the frequency.

The dynamics of a PLL are similar to damped oscillator systems, with a few different “types” of PLLs:

Type 1 PLL: XOR and RC LPF

In a simple implementation, one can simply implement the above with an XOR and and RC Low pass filter.

It is type I because it only has 1 integrator:

• The VCO

So it has one pole at the origin, and another pole at the RC corner frequency.

However, there are two drawbacks:

• Poor lock acquisition - A type 1 PLL often needs the VCO to be initialized close to the target, or else acquisition can be slow or fail without an initialization mechanism

• Non-zero static phase error in lock - In lock, a Type I loop typically requires a constant phase offset to sustain the DC control voltage.

Type 2 PLL: Charge Pump

The Charge Pump is a common block used that sources / sinks current into the filter.

Charge Pump PLLs are considered Type II because this system has 2 integrators:

• The VCO

• The Charge pump current pulses + loop filter capacitor that integrates current to voltage

There are two poles at the origin, and a zero formed by the R.

C2 is added as a high frequency bypass to reduce voltage ripples across Vctrl. C2 is usually smaller, about 1/10 or 2/10 of C1.

Type II integrators can drive steady state error to 0 even with a constant frequency offset, allowing for better tracking and acquisition.

Bode Plots Comparison for Type I and II PLLs

The open loops gains are different for type I and II. Notice how in the type II case, the R introduces a zero that adds phase lead (+90 deg), improving phase margin and stability.

The Transfer Function of the type II PLL

To design a PLL, one must first understand its dynamics through a transfer function. Note that C2 is neglected from this analysis because its value is small compared to C1.

In this derivation, the loop variable is phase, and gains are expressed in the usual PLL units (PFD/CP gain and VCO gain).

The open loop transfer function is given by:

To obtain a closed loop transfer function from an open loop form H(s) and Feedback component G(s):

Substituting H(s) into the above:

There’s a lot of terms here, but the key thing is that this is a second order transfer function of the form:

With damping factor:

And natural frequency:

If you recall second order transfer functions, the output “response” can be over or underdamped.

Now that we’ve seen the blocks and built some intuition, we can add additional layers of understanding on top of it. After the paywall we’ll define the common blocks that are used, define where noise and jitter show up, and give a high-level introduction to fractional-N PLLs.

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In the mean time, check out my other posts to see the systems that PLLs commonly interface with, as well as how to learn more efficiently:

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Editors note (6/1/26) - Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. I added links to additional posts I wrote that interface with Bandgaps after I originally wrote this one. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

However, I’ll leave this post free to get a flavor for the type of depth I go into.

A bandgap reference generates a stable voltage with low sensitivity to temperature, supply, and process (often with trimming).

Most IC datasheets specify that the IC will work within a specific temperature range (such as -55 ̊ C to 125 ̊ C). Variations in temperature can shift bias points and thresholds enough to break specs without a stable reference and proper matching.

Bandgap references are found in virtually all analog circuits as stable references for high-precision analog functions, such as ADCs, DACs, and comparators. They are also used to bias current mirrors for setting bias points so that the resulting circuit is robust to PVT variations. Because of their ubiquity, they tend to be reused and modified depending on the fab process and the level of precision required.

Bandgaps look simple, but are a delicate balance of a few fundamental analog principles, including:

• Matching: resistor ratios, BJT area ratios, amplifier offsets

• Feedback: Forcing ΔV_BE and setting I_PTAT robustly

• Temperature variation: How BJT and resistor characteristics vary over temperature, sometimes nonlinearly

• Trim & Calibration: Output accuracy, temp trim, and curvature correction

Below is a self-biased bandgap design example I built that illustrates these principles. I also have a fun side story at the end about how a group of young designers “competed” on who can make the best bandgap.

Circuit Analysis

Consider the Brokaw Bandgap reference in Fig. 1. The reference voltage is the output of the op amp. This circuit sums a PTAT voltage and a CTAT voltage:

• A PTAT voltage (Proportional to absolute temperature) means that the voltage increases with increasing temperature.

  • The PTAT voltage is generated by the BJT base - emitter voltage difference ΔV_BE = Vt*ln(n) by forcing two BJTs to operate at different current densities (often via an emitter-area ratio n). This voltage appears across R3 in the above example.

• A CTAT voltage (Complementary to absolute temperature) means that the voltage decreases with increasing temperature.

  • The CTAT voltage is generated across the base-emitter of the BJT which behaves like a diode. The reason behind this is related to the fact that the bandgap energy of silicon decreases with increasing temperature.

Additionally, the op-amp sets the PTAT current by driving the loop so its input nodes match (in the ideal case).

When both PTAT and CTAT voltages are summed with the right scaling, the first-order temperature dependence largely cancels, leaving a much flatter reference over temperature.

Derivation of Output Voltage

The derivation of the output voltage is as follows. Starting from KVL:

The current through the circuit flows through R2, where the voltage across it is the difference of the base-emitter voltages of Q and Q1:

Is is the saturation current of the diode. Substituting all of the terms:

The op amp uses negative feedback to ensure that I1=I2, so both terms can be cancelled. However, Is1 and Is2 are proportional to the cross sectional area of the BJT. Therefore,

where n is the number of BJTs in parallel for Q₀. The output voltage is given by:

The output voltage is the sum of a PTAT voltage (Vt) times a gain term and a CTAT voltage Vbe1. However, the temperature variations are not the same. The temperature variations of each term are:

The values in the term R3/R2*log(n) are selected such that the dV/dt of both terms cancel each other:

• n = 8 is common because 8 unit devices plus 1 unit device can be arranged symmetrically (e.g., a 3×3 array) to improve matching.

• The resistor ratio R3/R2 is selected to be equal to 5.5.

Using a bias current of 55 uA and Is1 = 6.734 fA from the SPICE model, and substituting all of these values in the equation above:

• Vbe1 = .59V.

• V_ref at 27 °C = 1.18V.

Circuit Schematic and Simulation Results

The circuit consists of the bandgap core which generates the PTAT and CTAT voltages. Both collector voltages are fed into an op amp which uses a PMOS differential pair as the first stage. This is done to avoid the VMIN problem an NMOS based op amp would experience since the common mode input voltage is approximately 1.18V.

The output of the first stage is fed into a second stage where the output is referenced to the VDD rail to control the PMOS current sources. The op amp is biased with a PMOS based cascode current mirror of 20uA. All of the DC voltages and currents are shown at T = 27 °C.

The simulation results of the bandgap reference are shown below.

Output voltage across temperature. The graph above shows the DC value of Vref as temperature swept from -55 °C to 125°C in 1°C increments. Ideally, the voltage should be flat across temperature, but the simulation shows the voltage follows a parabolic shape. The maximum voltage is 1.1885V which occurs at approximately 30 °C. The voltage drops for lower and higher temperature, where the minimum voltage is approximately 1.1869V. When the voltage is confined to this range, the maximum voltage difference is 1.6 mV, which is a variation of 0.14% over temp.

Line Regulation. This simulation sweeps the value of the voltage supply for three different temperatures: -55 °C (left curve), 27°C (middle curve), and 125 °C (right curve). The reference voltage stabilizes when the power supply has reached a certain threshold. This threshold is different for all three temperatures and is shown in Table 1. Once the power supply voltage has reached its threshold, the reference voltage is fairly stable.

Power supply rejection ratio, or PSRR. The PSRR is the ability for the circuit to reject noise from the power supply. It is defined as:

To perform this simulation, an AC signal of 1 mV was places in series with the power supply voltage. An AC sweep was performed for three temperature values from 100Hz to 100MHz and the magnitude of the output voltage was observed. The above formula was then applied to obtain the plots shown above, with results shown in table 1.

Mismatch in R10 Resistor. The resistance was swept parametrically from 5kΩ and 6kΩ in 100Ω increments and the output voltage is plotted. This simulation shows that for low resistor values, the CTAT voltage of the BJT dominates the characteristic, and the curve drops over temperature. When R10 is high, the PTAT voltage dominates, and the reference curves increase over temperature.

The following chart summarizes the simulation results.

Additional Features

There are additional features that bandgaps need:

Trim Range. The degree to how precise a bandgap has to be depends on the precision required across PVT. Monte carlo simulations are run to determine the untrimmed range over which the output voltage can vary, and trim features are added in appropriate places to ensure the output voltage can be turned to within spec across the temperature range.

Curvature Correction. Parts that operate in wide temperature ranges with tight specs can require additional “curvature correction” to improve the error across temperature. First order cancellation like resistor-only tuning can give residual curvature because parameters can have nonlinearities across temperature (such as BJTs) that affect the output.

Startup Circuitry. Because the core is self-biased, it has a zero-current equilibrium point, so startup circuitry is required to guarantee the intended operating point.

Story time: A Friendly Bandgap Competition

At an Analog Design internship, I once saw a group of young engineers have a friendly completion against each over who can design a bandgap with the highest accuracy across temperature. Work was to be done after 2-3pm on Friday so as to not interfere with day to day work.

Most of the “tricks” they experimented with involved:

• curvature correction techniques, like how to bias a transistor to turn on as a specific temperature, and where to place in the circuit

• NPN / PNP topologies

• value ratios (n, resistors)

• what current mirror to use (cascode, wide swing, source degenerated, wilson)

• what amplifier topology (NMOS, PMOS, gain stages, active loads) maximize gain and minimize offset

Each participant presented their results weekly and learned insights from each other to improve their day job, since analog is an art after all.

Conclusion

I feel like designing bandgaps are a really good introduction to analog circuit design because designing them develops a lot of the fundamentals used in more complex analog circuits.

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If you’re curious about how bandgap references are used in higher level systems, check out my other posts here:

References

[1] Timm, S. Wickmann, A., “A Trimmable Precision Bandgap Reference on 180nm CMOS”, Semiconductor Conference Dresden-Grenoble (ISCDG), 2013 International, 26-27 Dept. 2013, http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=6656292

[2] Hugo. “Bandgap voltage Reference” [Online]. Available: http://www.onmyphd.com/?p=bandgap.reference

[3] P. Miller and D. Moore. (2005). “Precision voltage references” [Online] . Available: http://www.ti.com/lit/an/slyt183/slyt183.pdf\

[4] A. Paul Brokaw. (2011). “How to make a bandgap reference in one easy lesson” [Online]. Available: https://www.idt.com/document/whp/how-make-bandgap-voltage-reference-one-easy-lesson-paul-brokaw

I think of analog design as one of the more "artful" branches of electrical engineering. It requires deep intuition, careful tuning, and a sensitivity to both device-level physics and system-level performance.

This post will be a survey-level overview of each of the major abstraction levels from system architecture to transistor-level design. I want to provide a “top down” perspective of what happens at each stage of the process, so you understand how your work fits into the bigger picture.

Note: My background is deeper on the design side than dedicated system architecture and verification. I’m aiming to describe both flows at a high level and keep details intentionally light.

System architecture and modeling

Product definition translates customer/market needs into requirements (performance targets, interfaces, constraints, operating conditions) that guide architecture.

Usually, the modeling begins with an “ideal” model of a high level system. Then, levels of fidelity are added to analysis the impact on the overall system performance. This enables architectures to analyze the feasibility of a proposed topology and catch system-level sensitivities - including noise, bandwidth, and mismatch — before specifications are handed off to individual blocks.

This level of fidelity include fab-specific models:

• Switching models of transistors to model anticipated loss

• Non-ideal components

System-level modeling tools shine at this level. These include MATLAB/Simulink, Simscape, Verilog-AMS, and SystemVerilog. They allow you to:

• Co-simulate analog and digital behaviors

• Evaluate loop stability (e.g., PLLs, regulators)

• Explore tradeoffs before committing to transistor-level design

Examples of such systems include:

• 3L Power Converter

• Serdes Transmitter

• RFIC superheterodyne Transmitter

In summary, you want to make sure any potential issues / spec defining features are verified at the highest abstraction level with as much fidelity as possible, before passing work down as specifications and requirements to low level blocks.

This process is done while specifying blocks at a high level, such as high speed SerDes:

Design + verification: two mindsets

After system architecture, the work gets split down into two “tracks” that coordinate tightly with each other:

Block level design: implement transistors in the given process through schematic entry and layout, and make sure they are robust against PVT and aging.

Verification: try to break assumptions and validate correctness across modes/corners/interactions (often using behavioral models + mixed-level sims + regressions)

The boundary between design and verification can be a little fuzzy at times based on the complexity of the chip. Sometimes designers end up doing verification alongside design. Other items there is a dedicated verification team that adopt formal verification practices from digital like UVM.

But can’t you just simulate transistors all the time? You can, but its computationally expensive. I want to stress three points:

• Transistor-level sims can be slow and unpredictable in runtime, which stretches the feedback loop.

• EDA licenses are limited and expensive

• Designer time is valuable and wants to focus on high level issues

In short, it is advantageous to use behavioral models if you can and simulate with Spectre when reasonable.

Behavioral modeling / co-simulation

Verification is becoming increasing important in the analog domain as well as complexity grows and simulations take longer to simulate.

Early on, teams build behavioral models of blocks to enable fast system simulation; later, those models get refined or swapped with transistor implementations as blocks mature.

Each transistor level block is “verified” by co-simulating it with behavioral models of the blocks it is supposed to interact with. The “config” view in cadence is used to swap out behavioral and transistor level views to get a feel for how blocks interact with each other. This way, one can ensure that the system behavior remains the same as transistors are slowly added.

Some teams borrow structured digital verification practices (UVM-style regressions, assertions/checkers, coverage mindset), adapted to mixed-signal.

How much behavioral modelling is needed depends on the complexity of the system:

• Behavioral modelling is not always required for standalone analog blocks (like an LDO for a processor)

• Behavioral modelling becomes much more important as more complexity is added onto chips, integration becomes tighter, and risk goes up of bugs.

There is an excellent paper to learn more about the design vs verification mindset called “Verification Mind Games: How to think like a verifier” [1] that I will direct you to learn more about.

It’s like the saying goes, “Trust, but verify”.

Transistor-level block design

I like to think about transistor level design as a multidimensional optimization problem. There are a dozen different paths you can go down to implement a specification, but you only have so much time.

Once block level requirements are defined:

• Start with a base circuit topology or existing IP that fits the function, speed, and power envelope

• Identify alternatives to topology - are there others that offer more benefits or improvements. You might look into research to identify promising ideas, or try your own.

• Optimize device sizes (W/L, resistor / capacitor values) to make your design robust

One key challenge is sizing components. Digital often pushes toward minimum dimensions for speed/area, while analog frequently uses longer L in critical devices to improve matching, gain, and noise. Here are some guidelines I’ve heard:

• Often 2-10X minimum L for current mirrors. Larger L values improve matching

• Size W based on current handling capabilities and gm for amplifiers

• Larger devices (W*L) sizes generally reduce Flicker 1/f noise

• Make capacitors large enough to reduce fringing effects

Scaling parameters can be used in schematic to keep device sizes ratios of each other and avoid any unnecessarily large devices. Sometimes, performance specs can be limited by devices sizes, especially on chip capacitors, so any devices need to be added externally.

At this level you’re dealing with “second order” effects from physics and variability, such as:

• Noise (thermal, shot, flicker)

• Body effect

• Short Channel Effects

• Matching

• Charge Injection

• Parasitic BJTs

In addition, you need to ensure that your design is robust against process variation, aging, and non idealities. This includes:

• Simulation across corners (PVT), layout parasitics, and aging (e.g., High Temperature Operating Life or HTOL) to ensure robustness

• Monte Carlo to evaluate mismatch/statistical variation.

• A Parasitic Extraction (PEX) at the end to verify overall circuit functionality

There are two key concepts analog people need to know: trimming, and test modes:

• Trimming. Trimming is when a value of a voltage in a circuit need to be adjusted due to process variation.

  • Monte Carlo simulations are used to evaluate the expected trim range of a parameter

  • Trimming is typically implemented with digitally selectable elements (e.g., resistor strings, current/Cap arrays, DAC trims), programmed via fuses/OTP/register settings depending on product.

  • The level of precision depends on how precise the value need to be to drive downstream blocks or for customer specs.

  • Global references (bandgaps, oscillators/PLLs) are common trim targets because many downstream biases and timings depend on them.

• Test Modes. Much analog functionality is hidden from the customer through “test modes”. Test modes can be thought of as “internal debugging tools” to obtain insight into what a circuit is doing at specific points. These add extra “probes” to analyze the actual circuit behavior and allows experiments to be run and observe. These are also “knobs” that you can turn to run various experiments. Typically, test mode values are written in registers that are hidden alongside the trim registers.

  Adding test modes help “future proof” your design against bugs by providing more probes and knobs to turn. If there are any weird bugs, especially in new IP, you have additional insight to look at to analyze behavior and compare against simulation expectation.

Block level design is where designer intuition matters most — knowing what to tweak and when, how to recognize subtle failures, and when to trust the simulation (or not).

A map of common analog building blocks

Here are some “Textbook” circuit topologies and IP blocks that commonly appear in analog design from the low level biasing to more system oriented.

Biasing

• Wide-swing cascode current mirrors

• Bandgap references

• Current Reference

• Low Drop Out Regulator

Switches

• Transmission Gate

Clocking

• Ring Oscillators

• Phase Locked loops

High speed

• Fundamental two stage op amp

• Folded cascode OTAs

• High speed comparators

• Gm-c Filters

High Precision:

• Switched-capacitor circuits

Power amplification

• Dickson Charge pumps

• Gate Drivers with series inverters

ADC / DAC:

• Charge Redistribution SAR ADC

• Delta Sigma ADC

Support:

• Common Mode feedback

• Level shifters

Once blocks are defined, they can be stitched together to construct more complicated systems.

I wrote foundational primers on several of these blocks here:

Conclusion

Analog Design is such a vast, field that many designers genuinely enjoy working in, but also challenging to understand without a mental model in your head to reference into the types of activities going on around it.

In summary:

• Start from the highest abstraction level

• Add fidelity as you can until you need it to save simulation speed and root out problems

• As more complexity is added, simulate transistor level performance using fab models against fab corners

• Simulate PEX near the end

  Silicon Co-Design is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber.

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I have several block level primers above, as well as an architectural breakdown of a high speed SerDes:

References

[1] J. Montesano and M. Litterick, “Verification Mind Games: How to think like a verifier,” paper presented at DVCon (United States), Mar. 4, 2014. [Online]. Available: https://cdn.prod.website-files.com/63f4bb21bd5303fe472ad00e/649596eab21cab357fc424b7_verification_mind_games_final.pdf

Most frustration in learning hard things comes from starting at the wrong zoom level.

I tried learning complicated things in analog design too early, like folded-cascode OTAs and PLLs in undergrad. I would get stuck fast — not because I wasn’t capable, but because I was being pulled into details before I had a mental frame to hang them on.

The turning point for me was realizing:

Complex topics don’t become easier when you memorize more details or view more lecture videos.
They become easier when you build better foundations and organize the details logically.

Here are the four moves I use to understand complex fields:

• Pick one foundation source (one teacher)

• Bottom-up summary (principle of operation)

• Top-down map (hierarchical outline of concepts)

• Relate advanced concepts from simpler ones (Folded Cascode OTA)

I’m going to use a few real analog design technical examples to make the method visible (because analog can get wonderfully complex).

Choose your foundation learning sources carefully

When learning a complex field, start with one “foundation source” that’s known for clarity, then translate it into your own mental model.

• In analog design, that might be Razavis book and lecture videos.

• In machine learning, that might be Andrew Ng’s Coursera courses.

The specific source matters less than the principle: pick one clear teacher, build your base, and then other authors start becoming more clear because you finally share the same “background assumptions.”

Once you’ve identified your foundation sources, the next step is straightforward: work through the material — read the chapters or take the course.

Bottom up Summary (Principle of Operation)

Read dense sections slowly and translate the author’s explanation into a “principle of operation” summary in your own words.

Example: Understanding Switching Behavior of a single transistor in Power Electronics

This method matters especially in power electronics, because switching waveforms can look intimidating at first glance.

A switching cycle has a lot happening in a short time:

• different devices turning on/off,

• different current paths,

• different energy transfers

all across multiple time intervals. If you try to absorb the full diagram in one gulp, it becomes confusing. Take the following switching diagram for a gate driver driving a single transistor:

So here’s what I do:

• I read the author’s explanation of how the circuit works. Typically this is very dense and has a lot of equations for rigor.

• As I’m reading, I break down the switching diagram into three intervals.

• In each time interval I’m writing a one line summary of what each voltage / current is doing.

  • T1: the “precharge phase” :

    • V_gs increases to V_th

  • T2: the “miller phase”:

    • V_gs increases slowly as V_ds transitions from V_bat to 0

  • T3: end of “miller phase” :

    • I_load reaches its peak

    • V_gs continues charging up to its peak value

• I bold important concepts to make them easier on the eye to reference later (like the “Miller plateau”.)

Here are my personal notes where I write the principle of operation in my own words as I went through this section the first time:

You might not explain the principle of operation the same way as me, but the point is that:

You summarize the material in a way you understand.

I have a post on the fundamentals of buck converters where I used this method to break down the principle of operations:

Top down - Hierarchical Breakdown of Concepts

I break down concepts broken down in a bullet format from high level concepts to low level ones that helps quickly “cue” the concept and retrieve the information I summarized earlier. This can apply to both architecture level and complex analog blocks

Here I will illustrate this with an ADC.

Example: ADC Architectures and Tradeoffs

I started reading the basics of ADCs on “Analog Integrated Circuit Design” and create a top level hierarchy of “textbook” topologies for various applications:

• ADCs

  • Low - medium speed, high accuracy

    • Integrating

    • Oversampling / ΔΣ

  • Medium speed, medium accuracy

    • SAR

    • Algorithmic

  • High speed, low to medium accuracy

    • Flash

    • Two step

    • Interpolating

    • Folding

    • Pipelined

    • Time-interleaved

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One popular ADC is the SAR ADC. Check out the important design considerations in this post:

Under each of these topologies, I expand into more detailed sub-architectures, including:

• The architecture block diagram

• The textbook transistor level implementation

• The important specs / design parameters

• The pros and the cons of the architecture compared to others

For example, here is my summary of the more general ADC “performance limits” section:

And here is an example of a section where I break down SAR ADCs, a very popular topology with a lot of research conducted on improving performance:

Once I have the map for a particular book, I started noticing gaps where I want more clarity on. I identify more specialized books in the area I am interested in and skim the table of contents to see if there is anything interesting. For example, I skim the table of contents for “Analog to Digital Conversion” by Pelgrom and make my notes on the chapter contents.

Then, once I identify a few specialized books, I purchase / borrow them and repeat the above process until I feel satisfied with the level of depth for the subtopics I am interested in.

This mental framework serves several benefits:

• You become adaptable. If your project changes or a new architecture shows up, you already have a mental frame to reference to understand new things

• You don’t waste time. You focus on the concepts that most improve your overall understanding.

• You can understand what people are doing in research and other fields, because you have a useful “starting point” to ask insightful questions

In short, what you don’t read is just as important as what you read.

Here are two posts that dive into more depth on ADCs as well as a high speed SerDes architecture breakdown that requires tradeoffs against different topologies to be weighed:

Arrange simpler building blocks to understand more complex ones

Once you get enough of a knowledge scaffolding for simpler concepts, its time to arrange simpler concepts into understanding harder, more “state of the art” ones.

Example: Understanding a folded-cascode OTA

Folded-cascode OTAs are very common building blocks used in a lot of systems due to their high speed, gain and bandwidth, but they are not easy to learn at first. Here is a “textbook” implementation of one:

Trying to understand this without prior understanding of building blocks is difficult. If you’ve taken a basic electronics course in undergrad, you can sort of make out what each transistor is doing, but there’s a lot of complexity here.

Fortunately, we can break down the “building blocks” that comprise a folding cascode into simpler blocks and combine them. These building blocks include:

• A conventional two stage op amp

• The wide swing current mirror

• The conventional cascode amplifier and the “folded” variant

Here are the block diagrams for each:

I do a principle of operation summary for each of these blocks with the above procedure, which I will not show here.

Then I do a principle of operation summary for the folded cascode OTA:

Now I am able to understand concepts like “low impedance nodes” as well as how to improve Bandwidth / Phase Margin because I understand the concepts from the simpler two stage op amp example.

In short, by understanding concepts for simpler blocks first, I am more likely to understand the principle of operation for more complicated, state of the art blocks because I have pre-existing context into what the simpler blocks are doing.

Summary

My rule of thumb is simple:

If you don’t understand the simpler topology, don’t jump straight to the state-of-the-art one.
Work backward. Identify what’s confusing, find the prerequisite concept, and rebuild from there.

A lot of people give up when something feels overwhelming — which is a shame, because most “advanced” ideas become very learnable once you’ve climbed the ladder in the right order.

These are just methods that work well for me. I’m sure others have great approaches too — and I’d love to learn them.

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If you’ve found a learning strategy that helps you understand hard technical subjects, drop it in the comments.

I also have several other posts if you want to continue learning about the design process of analog design and a few key blocks and systems:

References:

[1] “Circuit Diagram” (xkcd #730) by Randall Munroe — xkcd.com. Source: https://xkcd.com/730/ License: CC BY-NC 2.5 — https://creativecommons.org/licenses/by-nc/2.5/ Changes: Cropped/resized for header.

[2] T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design. John Wiley & Sons, 2011.
[3] B. Wicht, Design of Power Management Integrated Circuits. John Wiley & Sons (IEEE Press), 2024.
[4] M. J. M. Pelgrom, Analog-to-Digital Conversion, 2nd ed. Springer, 2013. (DOI: 10.1007/978-1-4614-1371-4)