This post will be an advanced deep dive of a state-of-the-art co-packaged optical system based on NVIDIA’s Dense-Wave Division Multiplexing (DWDM).

This post is organized in the following sections:

• What is Dense-Wave Division Multiplexing?

• A complete architecture breakdown of NVIDIAs DWDM with key physics constraints:

  • PIC - Ring modulator physics

    • Ring coupling theory - splitter and phasor theory

    • Key ring properties

    • How PN junctions shift the resonant frequency by changing the refractive index

    • Nonidealities - Thermal sensitivity and crosstalk

  • EIC - Clock forwarding and jitter analysis

    • Conventional clocking techniques - Forward clocking and embedded clocking

    • NVIDIA’s clocking architecture - half rate DWDM link architecture

  • 🔒 A Breakdown of the DWDM CW-DFB Laser Array and performance results

  • 🔒 Overlay of two critical spectrums that illustrate precise alignment challenges:

    • 🔒 NVIDIAs MRM transmission spectrum from the ISSCC paper

    • 🔒 NVIDIAs DFB Laser Array power spectrum from the ECTC paper

  • 🔒 A brief high-level overview of key CPO packaging features with TSMC COUPE

DWDM is fascinating because it blends together the knowledge amongst different specialties who all work together to create a successful product:

• The on-chip mixed signal SerDes designers designing the high speed TX and RX circuits

• The material scientists/solid state physicists quantifying the behavior of PN junctions and SiPh materials

• The packaging engineers who integrate everything together

The primary sources of this post are two NVIDIA papers on the circuit architecture and packaging aspects of DWDM from conferences I attended the sessions for in-person. These are:

• ISSCC 2026: “A 32Gb/s/λ 256Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3D-Stacked 7nm EIC/65nm PIC Technology”

• ECTC 2026: “Design and Packaging of a DWDM CW-DFB Laser Array for Co-Integrated Optical Interconnects”

I also integrate relevant material from relevant ISSCC forums and short courses as well.

I find that one of the best ways to learn more advanced concepts is to work backwards and figure out what simpler prerequisite concepts you need to learn first. The free half covers a huge technical breadth of material with links to several of my fundamental posts I wrote leading up to this. This way, people of all skill levels can work backwards and figure out what they need to learn to understand more complex concepts.

I want to challenge you to try to learn one new concept in depth from this post or my body of work, even if everything else doesn’t make sense.

Please note that I do not consider myself a photonics expert. I wrote this post using the sources listed above as sources-of-truth to base my commentary off of. If you’re an expert familiar with this material and notice a mistake in this post, please reach out to me so I can have this promptly corrected.

For a broad overview of optical communications, including VCSELs, optical modes, and key impairments, I recommend reading this post where I dive into these fundamentals in the free section:

What is Dense-Wave Division Multiplexing (DWDM)?

Optical interconnects in co-packaged optics help overcome the energy dissipation and frequency scaling challenges inherent in copper interconnects. Co-packaged Optics moves the optical engine as close to the chip as possible to minimize the length the electrical signal travels before being converted to the optical domain.

Optical communications enable low-energy and low-latency data transmission. However, optical communications is limited by a few constraints:

• The physical edge density. The optical signals need to be propagated through waveguides into a fiber optic connector. How and where the signal flows from the laser source to the electrical devices matters a lot.

• Frequency constraints of individual devices. The electrical as well as the optical bandwidths needs to be fast enough to handle the data throughputs needed.

Several companies propose solutions that push all available scaling dimensions. One of the most promising solutions to scale data speed involves densely multiplexing light signals of different wavelengths on the same waveguide.

Dense-Wave Division Multiplexing consists of individual optical channels of equally spaced wavelengths. Electrical signals are frequency multiplexed in a waveguide through a series array of micro-ring modulators. Ring modulators act like on-off switches for each of their respective channels. Ring modulators are ultra-compact, enabling many channels to be packed into a common waveguide.

Pros and Cons of DWDM

Compared to other modulation options, DWDM has several benefits:

• Scalability. DWDM performance offers scaling potential with the # and size of devices.

• Low latency for XSR due to no DSP

• High energy efficiency

• High bandwidth density

However, there are several challenges with DWDM that involve the material physics aspect of these devices:

• Temperature sensitivity. Lasers and MRMs are inherently sensitive to temperature and must be well controlled

• Design Complexity - DWDM moves a lot of the complexity from the electrical domain to the optical domain, and imposes unique clocking and jitter tracking challenges at high speed

• Laser Integration - DWDM needs a multi-wavelength laser source that has to be brought onto the chip

  Silicon Co-Design is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber.

Architecture Breakdown - EIC, PIC, Laser Array, and Packaging

Next I’ll discuss NVIDIAs DWDM multiplexing architecture. I’m going to describe the physics of the MRM on the PIC first to show how it works at a fundamental level. I’ll then discuss the clocking scheme of the EIC and show how the PIC requirements influence the EIC requirements.

At an architecture level, the job of an optical transceiver is to make sure that the data sent through an optical laser is received by a photodetector on the other end with acceptable BER. When selecting components, link budgeting is performed to take into account all sources of losses and optimize the performance of the entire system. I discuss link budgeting in the free section of this post:

PIC - Ring Resonator Physics

In a nutshell, microring modulators (MRM) accept or reject specific wavelengths of light going through a nearby waveguide. MRMs couple evanescently to nearby optical waveguides and act like band-stop/pass optical filters, depending on the way you look at it. Light is normally guided through an optical waveguide and passes right through, but the MRM acts like a low impedance for light at specific wavelengths.

MRMs consist of the following layers:

• A circular optical waveguide (grey) that is “sandwiched” between two regions:

  • p-doped region (blue)

  • n-doped region (red)

• A heater (green) that surrounds the MRM to regulate the temperature

A voltage source is attached to the n-doped region (yellow) to switch the optical signal going through the waveguide by shifting the resonant frequency over.

Lets dive into each of these elements in more detail.

Ring Coupling - the Splitter

The ring can be thought of as an splitter with two input and two output terminals. . Think of the ring like a “race track” that the coupled signal enters, runs laps around, and returns back onto itself until it ultimately decays due to losses.

In this splitter network, there are two constants that define the input-output characteristics:

• t is the transmission coefficient and represents how much of the signal gets through. Ideally, t should alternate between 0 and 1 at specific wavelengths.

• k is the coupling coefficient and is affected by how closely spaced the ring is to the optical line.

By conservation of energy, t^2 + k^2 = 1.

Once the optical signal enters the loop, it experiences loss and phase shift represented by a(λ). If the ring is unwound, the path of the light is represented by the phasor:

where the “a” term factors in the loss factor α and the propagation constant β that represents the wavelength-dependent phase shift:

The transmission formula is given by the ratio of the light that makes it through the optical waveguide vs the light coupled into the ring across wavelengths, which is given by:

Through substitution, as well as simplifying the phasor into a cosine, we arrive the following:

This formula lends itself to the following properties:

Rings Resonance Frequencies

In a microring modulator, the ring resonates when the diameter is equal to an integer number of wavelengths. These wavelengths is given by

where

• n_eff is the effective refractive index

  m = integer modes (1,2,3…)

  r = ring radius

Due to the periodic nature of the ring, the resonances are contained within a free-spectral range that limits the wavelength window signals can couple into it. Any signal outside of this window will alias into it.

One important property of the ring is the Full Width at Half Maximum (FWHM). This is the “width” of the resonance measured at half the max power (or 3dB on a log scale) at both edges of the resonances. FWHM is a useful qualitative reference to measure how “wide” the resonance is. This is given by:

The quality (Q) factor describes how narrow the resonance width is compared to the frequency it is centered at. This is given by:

where

• c is the speed of light in vacuum

  τ is the cavity photon lifetime that lumps in the above parameters

In NVIDIA’s implementation, the TX ring modulator quality factor Q is ~4.5K, and RX filter Q is ~4K.

In order to switch electrical signals into this ring, the ring bandwidth needs to be wide enough. The ring bandwidth is given by

where

• R is the ring junction resistance

  C is the ring junction capacitance

NVIDIA switches into each ring at 32Gbps, corresponding to a switching frequency of 16GHz.

PN Junction shifts the frequency by changing the refractive index

PN junctions normally act as electronic diodes that, electrically speaking, act as one way current flow with a small built-in voltage drop (~0.7V).

In conventional PN junctions, the p side is doped with type III elements (such as boron, gallium, or indium) with free holes in the valence band, and the n side is doped with type V (such as phosphorus or arsenic) atoms with free electrons in the conduction band. When a p and n material are sandwiched together, it creates a depletion region of “built-in” electrical potential due to the flow of carriers between the materials.

However, when PN junctions are used in SiPh, we care about the solid state physics properties that affect the index of refraction. In optical, these junctions are biased in reverse bias. As more voltage is applied to the n-doped region, the depletion region widens. This lowers the carrier concentration, causing the refractive index of the silicon to spike upward. This shifts the resonant frequency and moves it just enough to allow a light source to pass through. Think of this operation like a door opening and closing really fast.

In fact, these PN structures can be altered and routed in series with the optical signal itself. Distributed PN structures are used in Mach-Zehnder modulators that modulate travelling waves along long lengths and unique structures such as p-i-n are used in electro-optic modulators. Each structural variation has their own unique characteristics and tradeoffs. I discuss these options behind the paywall in this post:

Nonidealities

I’ll discuss two nonidealities of MRMs: Thermal sensitivity and crosstalk.

Thermal Sensitivity and Tuning Loop

Ring modulators are sensitive to temperature primarily because of the thermo-optic effect. The thermo-optic coefficient of silicon is ~1.8 x 10⁻⁴ K⁻¹ and changes in temperature affects the index of refraction.

Here, the thermal tuning loop measures the current at both TX and RX through:

• A drop-port photodetector (PD) at the TX to sense how much optical power is leaking out of the ring

• The TIA DC-loop at the RX

The PD current value is first digitized with an 8 bit SAR ADC, then processed digitally to produce a pulse density modulated signal to drive an integrated metal heater.

The paper doesn’t give too much detail beyond this, but I would imagine the ADC/DAC precision and loop bandwidth needs to be acceptable to correct for the expected temperature fluctuations with an acceptable wavelength error.

I dive into depth regarding the SAR ADC in this post:

Crosstalk

When multiple microrings are in close proximity to each other on the same substrate, cross talk is a key first-order phenomenon. The frequency characteristics of microrings tend to have long tails that poorly suppress sidebands and leak into other rings as well.

When deciding on what the Q factor should be, there is a tradeoff between crosstalk and the bandwidth:

• A higher Q lowers crosstalk and bandwidth

• A lower Q increases crosstalk and bandwidth

Modelling crosstalk is not that intuitive since there are many crosstalk paths among different rings that occur at different wavelengths.

Summary

Ring modulators appear simple at first but are highly affected by material properties and their tightly coupled nature. They are subject to device-to-device variation, so appropriate tuning circuits and control loops are needed to account for this, adding additional design complexity.

EIC - NVIDIA’s half rate DWDM link architecture

Now I will talk about the electrical side, more specifically the clocking architecture.

Of all the topics I’ve written about, I found that clocking is perhaps one of the trickiest subjects to explain in depth. As a simple analogy, think of clock synchronization like an orchestra conductor making sure all the instruments in the orchestra are in sync with minimal variation in when notes are played. There are many outside sources that can affect each individual musicians rhythm.

Each ring modulator is driven through their own SerDes electrical circuit. Compared to standalone high speed SerDes, each ring’s SerDes is slower and doesn’t have the DSP due to the XSR nature, easing some complexity. However, parallelizing 8 data lines requires synchronization and jitter control that adds additional complexity to the clock network.

Lets break down NVIDIA’s clocking architecture in more detail and see if we can make sense of this.

Conventional Clocking Techniques

When digital data is transmitted through a channel, there needs to be some way to clock the data at the RX to recover the data. There are two conventional ways of doing this:

• In a forward clocking scheme, the clock is sent alongside the data in a separate channel.

• In an embedded clocking scheme, the clock is “integrated” into the data stream. The data stream is serialized in a way that ensures enough voltage transitions (edges) occur to represent the timing information. This clock is then recovered at the receiver side through a clock data recovery (CDR) circuit.

I discuss the conventional circuits used in CDR circuits (such as bang-bang phase detectors) after the paywall in the following post:

No matter which scheme is used, each channel will couple in noise that appears as clock jitter, which is a deviation of the clock edge from its ideal location. There are two types of jitter:

• Correlated jitter - this is jitter that is generated from device operation such as TXPLL jitter and supply noise induced jitter. This jitter is identical lane to lane.

• Uncorrelated jitter - this is jitter that is random in nature, such as thermal, flicker, shot, etc, and is mostly generated through devices. This jitter is different from lane to lane.

Jitter show up as “tails” in the frequency content of a high speed signal. If jitter is high enough, it can degrade BER from the value being outside the threshold used to read 0 or 1. I discuss more about jitter in this post:

When clocking parallel channels, it is important to track the jitter and filter out unnecessary sources of it. In general, it is easier to track correlated jitter than uncorrelated jitter, and filter out low frequency sources of jitter.

There are a few pros and cons of each scheme:

• Forward clocking has excellent jitter tracking bandwidth, but requires a separate clock line. Additionally, uncorrelated jitter can accumulate.

• Embedded Clocking saves on IO, but CDR circuits have the potential to be exposed to jitter beyond its limited bandwidth.

DWDM has the unique benefit of embedding the clock in as a separate wavelength along the data lines, but is does come with a a few unique challenges:

• The data at the TX needs to enter the rings synchronously

• When data is sent down through the optical fiber, there will be delay mismatches due to various non-idealities such as chromatic dispersion and polarization mode dispersion.

• The thermal noise-induced jitter is dominated by the transimpedance amplifier (TIA) at the RX

Lets discuss what NVIDIA does to overcome these challenges.

NVIDIAs clocking architecture - half rate DWDM link architecture

NVIDIA uses a half-rate FC DWDM link architecture that embeds the clock inline with the data. In this architecture, there are 9 rings on each of the TX and RX that combines for a total data throughput of 256Gbps:

• 8 rings are for data at 32Gbps each

• 1 ring is for FWDCLK at 16GHz

On both the TX and RX side, the signal will traverse different lengths depending on which ring it coupled into. As a result, the TX clock needs to be de-skewed to account for known path length misalignment.

At the RX end, the transimpedance amplifier (TIA) adds a lot of thermal-noise induced uncorrelated random jitter. This TIA noise primarily comes from the feedback resistor (circled above) which is necessary to provide a low impedance input from a current sourced photodetector into the TIA.

To overcome these jitter challenges, NVIDIA uses an Injection locked oscillator (ILO) - based bandpass filter to bandpass filter the clock with BW ≈ 1-2GHz. This filters out jitter beyond 1GHz to remove most of the uncorrelated jitter and tracks most of the correlated jitter.

This clock is then distributed to the RX as illustrated by one example setting of the RX CLK distribution. Each RX has a local ILO that acts as another jitter filter. The clock distribution is segmented into two distinct spinal wires CLKA and CLKB that cut the capacitive load per wire in half. The RXPLL acts as a on-chip frequency synthesizer that provides the local timing reference upon startup until the system is locked to the main timing source.

I write about phase-locked loops in more depth:

DWDM Laser Source and Packaging of EIC and PIC

After the paywall, I will cover the packaging part that represents a major constraint in the physical realization of this system. I will cover the following:

• A breakdown of the DWDM CW-DFB Laser Array and performance results

• A brief high-level overview of key CPO packaging features with TSMC COUPE

In between these two discussions, I will overlay NVIDIAs measurements of the ring spectrum from the ISSCC paper with the DFB Laser Array from the ECTC paper, and discuss the challenges with aligning both of these. Alignment between these two spectrums is crucial across multiple devices because misaligned channels don’t transmit data.

Here are several other posts I’ve written that cover the fundamentals of advanced packaging in-depth:

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Editors note (5/31/26) - Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

Before each paywall, I’ll post links to some of my other adjacent posts that give you a well rounded flavor of the interactions amongst other domains.

Silicon photonics is one of the hottest and fastest moving markets to address high speed data demands in co-packaged optics (CPO) in AI data centers.

In this post I’ll cover a few important high-level details of silicon photonic circuits. These include:

• An Overview of the Link Budget and important considerations:

  • Laser Power

  • Connector Losses

  • Receiver Figures of Merit

• 🔒Key Figures of Merit for eye quality

• 🔒Validation Challenges (wafer screening and thermal stability)

  Inside the Silicon Machine is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber.

Link Budget

Understanding link budgeting is important to develop a system level understanding of a SiPh transceiver. Consider a typical electro-optical link with an external modulator:

At a high level, the job of a transmitter is to transmit the data at the specified data rate (224GPBS) with as low BER as possible in the given specification. Key system level performance specs include:

• Power efficiency: The ratio of energy consumed to the amount of data transmitted. This is usually measured in pJ/bit.

• BER: Bit error rate. Noise, loss and other effects degrade bit error rate. Requirements range between 1e-4 and 1e-6 depending on the standard.

A laser source (whether that be generated on board or coupled in externally) provides the power and is sent through a lossy modulator, connectors, and waveguides.

This power is then sent through the optical channel, converted back to a weak electrical signal through a photodetector, and amplified by a transimpedance amplifier. The signal at the RX need to be high enough compared to the noise in order to be able to detect the signal properly.

All of the sources of loss in between the TX and RX must be quantified for in a link budget in the optical chain. Lets break down each part.

Lasers

Lasers are either integrated within the PIC or coupled in externally. These external lasers are coupled into the chip through edge couplers or grating couplers.

There are a few important specifications:

• Power: The amount of coupled power is limited by two-photon absorption and other non ideal effects. Shown is a sweep of Pin vs Pout where Pout saturates and a high enough Pin can cause passivation melting:

  

• Relative intensity noise (RIN) - Rin refers to the relative intensity fluctuations of the optical signal of a laser source. This is a critically important parameter in PAM4 schemes because PAM4 has much lower noise margin than NRZ. A high RIN raises the noise floor causing a higher BER. RIN is given by:

Companies with lasers in the value chain include Lumentum, Broadcom, Coherent, Sivers, Scintil, Xscape, and Quintessent.

Losses in Connectors

There are several loss sources in the connectors themselves. These include:

• Modulator loss - due to intrinsic optical absorption and scattering

• Multipath Interference (MPI) - Optical reflections from multiple connectors / discontinuities

• Polarization Dependent Loss (PDL) - Measures loss due to change in signal polarization

Receiver

On the receive side, the signal is detected by a photodetector. This weak signal plus a noise signal is converted to a voltage through a transimpedance amplifier (TIA) that converts current to voltage.

A few key specs here are important:

• Responsivity - Measures how effective the photodetector converts photons to electrons. This is typically measured in A/W.

• Dark current - Measures the current flow when no light is present. Defects can cause high dark current that adds noise to RX and reduces sensitivity.

• Input-referred noise - assesses the noise floor of the TIA.

• Transimpedance Gain - measures the electrical strength of the receiver. TIA gain is very important because if TIA gain is too low, output voltage swing will not be high enough to compensate for noise. It is given by:

• Receiver sensitivity - the minimum optical power required to achieve a specific BER target. This is determined by plotting RX BER vs OMA. BER goes down when received optical power goes up.

• THD (Total Harmonic Distortion) - quantifies the non-linearity of the TIA. This affects PAM4 because it affects how even spaced out each of the four levels are after optical to electrical conversion.

Eye Quality

After the paywall I’ll go into key parameters that define the eye quality, practical challenges when scaling production of SiPh, and NVIDIA’s approach to thermal tuning design.

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If you’re curious to learn more, check out my other posts here:

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Editor’s Note (6/1/26): Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth and combination of the synthesis involved, the deepest technical layers of my guides will now be reserved for paid subscribers.

Before each paywall, I’ll post links to some of my other adjacent posts that give you a well rounded flavor of the interactions amongst other domains.

In this post I will cover entire optical communications space:

• I will introduce the conventional IM-DD optical approach with VCSELs used for short reach

• I will then highlight challenges with scaling conventional IM-DD to higher data rates

• Then I’ll explain techniques to improve data bandwidth:

  • 🔒 Co-packaged optics

  • 🔒 Silicon photonics

  • 🔒 External modulation

  • 🔒 Coherent optics

High speed optical interconnects have become one of the hottest markets in AI data centers. As bandwidth demand rises, the challenge is no longer just computing on data faster, but moving it across packages, boards, racks, and clusters efficiently.

The optical space has exploded over the past few years with many companies and startups proposing solutions to tackle data demands.

But I want to step back and ask ourselves: what are the first principles challenges with scaling high-speed optical communications?

The workhorse for short reach - IM-DD & Pluggable Optical transceiver

The workhorse for short reach optical communications today are IM-DD with pluggable optical transceivers. Lets take a looks at what each consists of.

Intensity Modulation - Direct Detection

IM-DD is the workhorse of short reach optics. IM-DD encodes information in optical intensity (whether that be 0/1 or higher levels in PAM4) and recovers it through direct detection.

This intensity modulation can be performed in one of two ways:

• Direct modulation - the laser is turned up/down by the electrical signal

• External modulation - a driver modulates a steady optical carrier

Pluggable Optical Transceivers

These IM-DD are typically packaged into pluggable optical transceiver modules that sit far away from the chip. These are are match-box sized modules that take in electrical (client) side data and convert it to optical (line side). Each block consists of following:

• Serdes + DSP - For serializing / desterilizing the data from/to host and perform equalization

• EIC - Electrical integrated circuit - consists of the electrical circuits fabricated in electrical processes (drivers, mixed signal conditioning, etc)

• PIC - Photonic integrated Circuit - consists of the optical circuits fabricated in optical processes (Si Photonics, VCSELs, etc)

Optical transceiver modules are a very mature technology that has scaled in data throughput for many years. However, with AI workloads demanding 224+ GPBS throughput capability, the performance of the optical transceiver itself needs to adapt, as well as the signal integrity between host die and optical engine.

System architecture breakdown of a IM-DD

Next I will break down the architecture of an IM-DD in each of its components:

• Transmitter

• Fiber

• Receiver

I will discuss several options for each and important design considerations.

TX Driver - Direct Modulation

Laser (Light amplification by stimulated emission of radiation)

Lasers are powered by a large pump current stimulating emission. Photons with energy close to the material bandgap interact with electron - hole pairs and cause identical photons to be emitted. This causes an “optical gain” of photons within the active region.

This photons is then confined using two mirrors: one opaque, and other that is semitransparent to allow the light to shine through.

Lasing occurs when the pump current is high enough such that optical gain > optical losses.

Then, either a cavity structure or frequency selective bragg reflectors selects which optical modes are sustained.

In a Distributed Feedback laser (DFB) laser, a periodic grating of Bragg reflectors provides wavelength - selective optical feedback, favoring a narrow lasing wavelength. These Bragg Reflectors are highly tunable depending on the index of refractions and the lengths and # of sections.

VCSEL (Vertical-Cavity Surface-Emitting Laser)

VCSELS are lasers that emit light vertically in a circular cross section. The active region consists of multiple quantum wells that enhances optical gain. Distributed bragg reflectors are stacked on the top and bottom of the active region with alternating refractive indexes. These layers are fabricated using epitaxial growth on a substrate.

The light is then confined with an oxide and current is pumped in through pads. The light is shown vertically above and redirected toward the optical fiber with optics.

The Pout/I of VCSELs almost resembles a linear diode. The VCSEL begins lasing above a particular threshold current and exhibit a linear relationship between Pout / Iin over a useful operating region. Lasers require a DC bias to set the device in the linear region.

One important parameter is the extinction ratio, which is the ratio between P1 and P0. A higher extinction ratio is preferred as it improves BER margin to detect teh signal at the other end, but higher extinction ratios require higher currents, and therefore power, to drive the device.

The two major materials used in lasers are GaAs or InP:

• 850 nm GaAs VCSELs are common for short-reach multimode links.

• 1310/1550 nm InP-based lasers/modulators are common where single-mode fiber, longer reach, or telecom/datacom bands matter.

VCSELs are very popular in short reach communications for a numbers of reasons:

• Low cost manufacturability - they are easy to test on-wafer across multiple samples

• Scalability - they can be formed in “arrays” to drive multiple optical lanes

However, VCSELs do have some drawbacks:

• Reliability - issues due to oxide confinement and high currents degradating mean-time-to-failure

• Signal switching nonidealities, including:

  • Turn on delay- a delay in the turn on of the signal that adds to latency

  • Jitter - uncertainty in the signal edge that degrades BER

  • Relaxation oscillation - an “underdamped” response in the turn-on characteristic that can affect BER and signal quality

The main tradeoff in VCSELs is between BW and reliability. Higher current densities allow for higher BWs, but it also decreases the mean time to failure, a common metric used when evaluating reliability.

Driving the Laser

Here are a few DC coupled, common anode circuits used to to drive the laser directly using either fully differential or pseudodifferential to convert a voltage to a current to drive the VCSEL. There are other methods of driving such as common-cathode, BJTs, and push-pull implementations depending on the requirements of the system.

In general, the more VCSEL current that is needed, the slower the driver will be due to increasing output capacitance.

Fibers

Multimode fiber optic cables are primarily constructed from silica glass (silicon dioxide). There are two major categories of fiber for high speed communications:

• Multimode - Uses a larger core (50–62.5 um) to transmit multiple light paths

  • There are five classifications, OM1-5, that grade the quality of the fiber.

  • Pros: Cost-effective for short-distance, high-speed applications

  • Cons: Limited distance due to higher signal modal dispersion

• Single Mode - Uses a smaller core (8-10um) to transmit a single mode of light

  • Pros: Low signal loss, avoids modal dispersion

  • Cons: Higher cost of laser components and more complex installation requirements

Generally speaking, multi-mode fibers are used for short reach interconnect due to its low cost and complexity. However, single mode fiber is being evaluated to “future proof” the data communications since it can support the higher BWs, though it adds to cost and integration complexity.

There are also four wavelength bands used in the fiber:

• 850nm band - used for short reach links

• O-Band - 1310nm

• C-band - 1550nm

• L-Band - Extends C band to allow 2x network capacity

There are four major impairments:

• Loss. Losses cause pulse attenuation after propagation from a fiber. These are caused by intrinsic sources, including

  • Rayleigh Scattering

  • Absorption

  • Manufacturing Stress

• Chromatic Dispersion - pulse spreading after propagation over the fiber. This is caused by fiber refractive index dependence on wavelength

• Modal dispersion - distortion due to different propagation delays of different optical modes. Modal dispersion matters in multimode fiber.

  

• Polarization Mode dispersion (PMD) - dispersion cause by pulse spreading of different polarizations due to asymmetries in the fiber core.

Receiver - Photodetector

A photodetector consists of a Reverse biased PIN junction that generates current proportional to the detected light. The transimpedance amplifier then amplifies this current to an output voltage at the other end.

There are some important specs of this system:

• PIN characteristics: Responsivity, capacitance, noise, dark current

• Receiver Q-factor: The received signal level relative to total receiver noise

• BER: BER can be derived from this Q factor: BER = 1/2*erfc(Q/sqrt(2))

A higher extinction ratio is desired to ease the burden on the receiver, but it does come with a higher power usage.

Why Scaling IM-DD is hard

Scaling IM-DD to higher data throughputs is hard due to several unfavorable tradeoffs between BW, reach, noise, power, SNR, and cost. These include effects in both optical and electrical domain themselves:

Optical

• Chromatic dispersion

• Polarization Mode dispersion (PMD)

• Nonlinear and interference effects

Electrical

• Noise penalties at Higher BW

• Tighter jitter, skew, and ISI

• BW scaling limits in front ends

You can have the fastest optical transceiver, fiber, but its pointless if the signal can’t get to it fast enough. Not only the optical receiver itself needs to improve, but the signal integrity from the electrical interconnect is running into challenges shuttling high speed data back and forth. Solutions need to ensure that speed “bottlenecks” within the system scale with the system demands.

This leads to four major trends that generally increase complexity:

• Co-packaged optics - embedding optical components within the package itself

• Silicon Photonics - routing light through silicon waveguides and modulating it

• External modulation - modulating a continuously running laser for higher BW

• Coherent Optics - modulation amplitude and phase in the optical domain

After the paywall I’ll discuss these in further detail.

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If you want to learn more about how optical communications interfaces with adjacent domains, consider checking out these other posts:

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Editor’s Note (5/30/26): Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth of the synthesis and combination of topics involved, the deepest technical layers of each of my guides will now be reserved for paid subscribers.

Before each paywall, I’ll post links to some of my other adjacent posts that give you a well rounded flavor of the interactions amongst other domains.

As data speeds climb from 112Gbps to 224Gbps and 448Gbps, data starting running into physics constraints and transceivers become more complex to compensate for these effects.

In this post I’ll be doing a system architecture breakdown of a modern DSP-based transceiver. I’ll explain the underlying physics constraints and the major blocks data passes through. Then, I’ll do a deep dive into the high-speed building blocks (shown in yellow) on the TX and RX side. I’ll be covering the following:

• The real problem: increasing data throughput under physical limits

• System Datapath overview

• TX Architecture:

  • Serializer / Mux tree

  • DAC - 6-7 Bit current steering DAC

• RX Side - Time-Interleaved ADC

• 🔒Clocking Architecture

  • 🔒Clock Recovery: Bang Bang Phase Detector

  • 🔒Clock Generation: LC-VCO Based PLL

  • 🔒Multi-phase clock generation: The phase Interpolator

  • 🔒Clock Distribution: Repeater, transmission line, and resonator-based

Most of the figures in these slides are from the ISSCC tutorials as well as the papers in the references.

The real problem: increasing data throughput under physical limits

As data rates climb, we need to ask ourselves: what fundamentally constraints the data speed from first principles?

Data speed is now limited by physics and device parameters on the chip, which include, but not limited to, the following:

• Channel Loss: Loss scales with signal frequency, and high frequency attenuation rounds out the sharp edges of digital signals

• High impedance nodes in analog circuits: Active loads have a high input resistance, which is good for gain, but also creates dominant poles that lower overall BW.

• On-Chip Capacitance: Bigger transistors have bigger C that can affect rise/fall times of signals

• Noise / Jitter: The randomness in clock / data edges affect how fast those signals can be relative to the clock period. This impacts reliability of high speed digital circuits and time-interleaved switches

What tricks do designers have to increase speed? I contend there are two major paradigm shifts:

• Current steering circuits: These circuits steer constant currents through switches to a resistive load. The main advance is that it minimizes charging/discharging time of parasitic capacitors. However, current steering circuits tend to consume more power than equivalent charged-based topologies.

• Time interleaving: Instead of making a single component faster, place many in parallel and distribute data through “ranks” of S/H and T/H switches. Time interleaving introduces added complexity in clocks to coordinate parallel operations

System Datapath overview

Next lets look at the major blocks in the datapath.

The function of a transceiver is quite simple: transmit a large amount of data from the TX and RX with minimal errors across a medium as fast as possible.

For short reach, low speed operation, the architecture relied mostly on analog blocks. However, due to recent data demands, one of the big paradigm shifts is a move to digital for the processing. Digital is great at performing parallel processing of data at a moderate clock (1-10’s GHz) frequency.

However, when it comes to data transmission, edge density becomes the constraint. You can only pack so much circuitry to drive the parallel channels on the edge of a chip and copper cables in the system.

As a result, data transmission favors serialized data at a high speed to pack as much data density as possible and transmit on a single cable.

These constraints influence the architecture of modern wireline transceivers.

On the TX Side, the main high speed blocks include:

• Forward Error Encoding (FEC) - Encodes the data with parity bits that correct for channel error at the RX side

• Feed Forward Equalization (FFE) - Pre-distorts the signal using a FIR filter to compensate for channel losses

• Serializer - Serializes the digital data from multiple channels and raises the effective output rate. 112 Gb/s PAM4 corresponds to a 56 GBd symbol rate, though practical serializers often use half-rate or quarter-rate architectures that are time-interleaved

• High-speed DAC - turns digital symbols into an analog waveform

• Driver - amplitudes the signal before it is transmitted on the channel

In the Channel:

• Matching network - matches the TX and RX to the characteristic impedance to avoid reflections and transmission line effects

• Channel - attenuates and distorts the transmitted signal

In the RX:

• Receiver front-end - conditions the signal by amplifying it (variable gain amplifier) and providing equalization (CTLE)

• TI-ADC - converts the analog value to digital values

• Deserializer - converts the digitized data from the transmission rate to the digital frequency

• DSP - processes and recovers data

As a result of the added digital complexity, high speed and parallel processing blocks require a robust clock architecture to synchronize the data properly.

In the following sections, we’ll step through each of the high speed blocks, with the principle of operation, the key impairments, and how they affect the system level.

TX Architecture

Serializer / Mux tree

The mux tree is used for serializing / deserializing data. Here, stages of 2-1 muxes are arranged in ranks. This ensure each interconnect between muxes aren’t heavily loaded that can slow down operation.

The final rank operates with the highest-rate clock, while earlier ranks use divided versions of that clock so that each stage runs at a rate compatible with its local data rate.

A common high-speed mux cell is the current steering mux cell. This cell uses two differential pairs for each of the inputs. To select each input, the SEL signal, synchronized to the CLK, steers the current between the two input branches.

Impairments

• Kickback noise from clock feedthrough. Clock feedthrough and switching transients can disturb internal common-mode nodes and degrade timing margin, especially in the final high-speed stages.

• Skew between SEL and clk.

• Skew between stages in the MUX tree. The accumulated clock delay associated with the driver and the mux itself can cause ranks to fail to clock the data fast enough.

DAC - 6-7 Bit current steering DAC

The high speed DAC commonly employs a segmented current steering architecture. This architecture uses scaled current sources representing the “weight” of the binary bits. The steered currents are summed and converted to an output voltage across a load impedance.

The current steering cell consist of two main branches and a selector with a flip flop and driver. This current source is generated from the bottom two transistors. The driver cell “steers” this current between two branches: the left branch to enable the bit and right branch to disable it. The switch control is retimed so current steering occurs with precise timing at the symbol rate.

Current continuity is often preferred for high speed because it minimizes voltage swings from constantly charging / discharging capacitive nodes. However, it also consumes static power even when the bit is disabled.

This current cell is then scaled to a segmented architecture, which uses both unary and binary DACs. Unary (or thermometer code) uses unit-sized current sources arrayed in a 2x2 grid in layout to achieve better matching of current sources.

In many wireline transmitters, DAC resolution is kept modest, often around 6–7 bits, because channel loss, jitter, and front-end noise dominate before very fine quantization does.

Impairments

There are several impairments that cause both timing and amplitude errors:

• Time delay

• Voltage glitches

• Clock Skew

• Finite Input impedance

• EMI at all sources

  

These impairments introduce timing and amplitude error at the system level. They translates to jitter in the x domain and noise in the y dimension. These effects directly affect the size of the “eye” at the RX side, so it is important to account for these and spec these appropriately.

RX Side - Time-Interleaved ADC

A common modern RX approach uses time-interleaved asynchronous SAR ADCs operating in a self-clocked manner.

In normal asynchronous SARs, it takes N clock cycles to complete an N bit conversion. In asynchronous circuits, self-clocking allows the completion of one comparison to automatically trigger the next.

Self-clocking removes the need for a very high external clock, but it makes the conversion timing dependent on timing delays and handshake robustness.

Asynchronous SARs are commonly used due to low comparator count, simple digital logic, and capacitive DACs for energy efficient operation at typical 6-7 bit resolution.

These SAR ADCs are time interleaved. The high speed data is “fanned out” to each of the sub-ADCs in order for their analog values to be digitalized. This is accomplished through a two-rank NxM interleaving scheme. This architecture performs sampling in two ranks:

• Rank 1 - Track and hold. The first rank tracks and holds the signal. The performance of these switches are critical as they sample the full BW signal.

• Rank 2 - Sample and hold buffer. These buffer the T/H signals to drive the parallel ADCs.

In modern PAM-4 112Gbps, the interleave factors range from 36-128 sub-ADCs depending on the layout area, with 64 being common. [1]

Impairments: There are several impairments:

• Skew and Jitter of clock

• Mismatches between sub-ADCs

These impairments translate timing mismatches into sampled voltage errors, often in a signal-dependent way, and can create both noise-like degradation and spurious tones.

Clocking Architecture

Perhaps the most important part of a high speed chip is the one everyone takes for granted: The clock.

The clock distribution becomes an increasingly important constraint as dimensions and speeds have scaled down. There are several challenges the clock faces:

• The clock needs to be recovered from the asynchronous RX data to ensure that the clock is in “sync” with the data to clock it appropriately

• The VCO needs to generate a reference clock with low jitter

• The time-interleaved blocks need some form of multi-phase clock to synchronize operations across parallel processing elements cleanly

• The parallel clock distribution needs minimal skew to minimize mismatches

After the pay wall I’ll describe the clocking architecture in more detail.

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If you want to get a flavor for the adjacent domains involved, I have several other posts to check out as well:

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Editor’s Note (6/1/26): Moving forward, I am transitioning this Substack into a deep-dive resource on System Architecture that covers the packaging, thermal, power, and signal integrity stack. To reflect the depth and combination of the synthesis, the deepest technical layers of my guides will now be reserved for paid subscribers.

In this post I cover the following topics:

• SerDes - The Workhorse of chip to chip communication

• The Root Causes of Signal-Integrity Degradation at High Speed

• How Channel loss and Jitter degrade Bit Error Rate

• Major System Trends:

  • PAM-4

  • DSP-based Architectures

• 🔒Error Reduction Techniques

  • 🔒Forward Error Correction

  • 🔒Equalization

    • 🔒TX - Pre-emphasis / FFE

    • 🔒RX - CTLE and DFE

• 🔒How to Achieve Higher Data Rate

Everyone talks about the importance of chip-to-chip communication, but few people appreciate the complexity hiding underneath it.

Signal integrity and SerDes architecture are often discussed as if they belong to different worlds: one in the lab and on the board, the other inside the chip. In reality, they are deeply coupled.

My goal in this post is to show how signal-integrity constraints at the channel and board level—loss, jitter—affect performance through BER and ultimately drive complexity back into the transceiver itself, shaping choices in equalization, clocking, and data conversion. Here I’ll focus on the signal-integrity foundations from first principles, then build on that in a follow-up post on chip architecture.

Much of the content of this post is material consolidated from a Tutorial given by Dr. Mike Peng Li from DesignCon 2026, the premier high-speed communications conference, as well as from ISSCC, academic papers and SI books. Figures are reproduced for commentary and educational purposes.

SerDes - The Workhorse of chip to chip communication

A serializer-deserializer (SerDes) converts parallel digital data into a high-speed serial stream for transmission, then reconstructs it at the receiver. This allows systems to move large amounts of data between chips and systems without requiring a huge number of parallel wires.

SerDes and optical links are the “workhorses” of communication within data centers in “scale up” and “scale out” networks:

• Chip to chip

• Modular top chip copper links on a PCN and an optical module

• Between a CPU and network interface

• Backplane and midplane links over backplane PCBs or passive copper cables

SerDes is what enables parallel computing across many CPUs and GPUs as a means of data distribution.

Historically, many SerDes architectures have been analog-based. SerDes speeds have scaled with PAM-2 (NRZ) signals over time to meet the growing needs of traditional computing.

Then, AI and chiplets came in and started demanding more data.

These two technological trends put a lot of pressure on chip-to-chip communication to get faster and reach farther due to the massive amounts of data movement:

• AI workloads involve massive data movement: repeated memory access, movement of intermediate results, and parallel processing across many GPUs in a rack.

• Chiplets disaggregate a system into multiple smaller dies, which must then be tied back together through high-speed chip-to-chip interfaces.

However, as data demands push speeds higher and links longer, fundamental physics begins constraining performance:

• Channel loss due to higher attenuation at higher frequencies

• Jitter budgets getting tighter

• Transmission line effects that cause distortions

• Noise that can cause errors

These add complexity to the SerDes to correct for. Unfortunately, the added complexity makes it more challenging to understand how one part of the system affects the other, such as:

• How jitter in the VCO eats into the timing margin needed to meet the target BER

• How receiver clock skew and TI-ADC area constraints affect sampling margin, data throughput, and calibration burden

In the following sections I’ll be focusing on signal integrity fundamentals from first principles. The goal is to ask:

• What are the fundamental physics constraints limiting performance?

• What complexity in the chip architecture is needed to scale speeds beyond 112.5Gbps to 224Gbps and eventually 448Gbps?

The Root Causes of Signal-Integrity Degradation at High Speed

In this section, I’ll focus on describing two primary causes of signal-integrity degradation at high speeds: channel loss, and jitter. I’ll then show how they affect BER.

Channel loss in Copper interconnects

Copper is widely used as the interconnect of choice to transmit signals between chips due to its high electrical conductivity and durability.

Copper has been used for many years at low data rates where the losses were much less. However, the loss increases at higher signal frequencies. There are two major loss mechanisms:

Dielectric loss. Dielectric loss occurs due to heat energy dissipation of dipoles at high frequencies. A quickly alternating electric field in the dielectric causes polarization in dipoles in the dielectric (i.e. the positive and negative parts of the atom move apart) and results in energy dissipation through heat.

Dielectric loss scales with frequency and is generally the dominant loss mechanism at the data rates that modern SerDes nowadays run at.

Skin effect. Skin effect occurs when time-varying electromagnetic fields push current toward the edges of the conductor. This results in an effective lowering of the cross-sectional area that the signal actually “sees”.

Skin-effect loss scales roughly with the square root of frequency and has historically been a major source of channel loss until dielectric loss becomes more dominant at higher frequencies.

In both cases, signal attenuation increases with frequency. This means that signals with multiple frequency components like square waves will have higher order frequencies attenuated more strongly. This will result in a “rounding” of the signal at the other end with degraded amplitude.

Modern 112G PAM4 systems typically target 25 dB to 35 dB of channel loss.

Jitter

Jitter is defined as the time variation in when a signal edge actually transitions compared to its ideal transition point. Jitter is a significant limiter of performance in high-speed applications because it affects how much of a time ”window” you have to accurately sample the digital data.

Jitter is broadly broken down into two major categories: Random and Deterministic:

Random Jitter comes from noise-like mechanisms that are fundamentally statistical in nature, such as thermal noise.

This is always uncorrelated and typically modelled as a Gaussian distribution due to the central limit theorem that states that summing up a variety of PDFs from uncorrelated sources tend toward a Gaussian distribution.

Deterministic Jitter is jitter from repeatable structure in the system such as data movement and reflections.

This jitter is typically bounded with a max and min timing shift - the edge shifts in a repeatable way. It can also be correlated or uncorrelated. Examples include:

• Data dependent jitter (ISI) - Symbols from previous transitions spill into the next time window

• Periodic Jitter

• Bounded uncorrelated jitter

As link complexity has grown, many other jitter sources must be accounted for during design and measured in silicon.

How Channel loss and Jitter degrade Bit Error Rate

Both losses distort the signal in complementary ways:

• Channel loss distorts the waveform itself by attenuating and smearing its higher-frequency content

• Jitter introduces uncertainty in when transitions occur.

Together, these (and other effects such as reflections) reduce eye opening and increase the Bit error rate (BER) at your sampling edge.

Bit error rate is not easy to measure directly because of the amount of time it takes to observe enough samples (sometimes trillions) to get a statically significant measurement of BER. It is usually easy to measure a BER of 10^-6 which is 1 error in 1 million bits with a BERT (Bit error rate tester), but some systems require BERs of 10^-12 which is one error in one-trillion bits!

Often, lower BERs are often extrapolated from higher BER curves. The Dual-Dirac model is a widely accepted “worst case model” used to extrapolate this. To show how BER is driven from jitter, consider the two major classes of jitter:

• RJ spreads the signal edge according to a Gaussian distribution

• DJ shifts the signal edge with two “bounds”. In this model, the worst cases are represented as two worst case impulse ”spikes” at either bound.

  (Note that this is not the actual PDF of the DJ as it varies in uniformity within the bounds. However, this works fine because we only care about the “tails” of the RJ curve convolved at the bounds)

These two sources combine in a “convolution” format, so the gaussians of the RJ map onto the bounds of the DJ to obtain the Total Jitter (TJ). The BER is then estimated from the tails of the total-jitter distribution: as the distribution spreads further into the sampling margin, the probability of error increases.

You can then use this to map contours of constant BER in the center of the eye that decrease the more the signal is sampled at the center of the eye:

Major System Trends: PAM-4 and DSP-based Architectures

PAM-4: 4 level pulse amplitude modulation

PAM-4 uses four levels of modulation instead of two. This allows you to transmit two bits per symbol while halving the required symbol rate for a given bit rate.

However, added signal levels make PAM-4 more sensitive to noise, nonlinearity, ISI, and timing jitter. It also requires DACs to generate the four analog levels. There are also more transition combinations to account for.

DSP-Based Transceivers

When data speeds were slower, most of the processing came from analog circuits that were sufficient to perform the signal conditioning needed to achieve good BERs. Figure 9 shows a typical short-reach, analog-based transceiver with common building blocks.

As speed and throughput increased, most architectures added a lot of DSP along with the analog blocks. Digital allows a lot more programmability to handle data processing with FIR/IIR filters. However, digital also adds a large amount of peripheral complexity to handle the speed it needs, including:

• The ADC/DACs needed to convert between the analog and digital domains

• The clocking architecture to clock the circuits

Error Reduction Techniques

After the paywall, I’ll cover key error reduction techniques, including equalization, FEC, CTLE, and DFE.

If you want to continue expanding your knowledge related to signal integrity, including why modern SerDes is so complex, check out my other posts:

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