Editors Note (6/23/26) - The last half of the post will be paywalled. Before each paywall, I link several of my other posts in domains adjacent to the topic you are reading to give you a well rounded flavor of the areas adjacent to packaging.

At ECTC 2026, TSMC noted that many package designers are being too aggressive with their package designs and that a lot of communication is needed to balance the design performance with the manufacturing and reliability constraints of the package.

This post helps reduce that communication overhead.

In this post I’ll be diving into the key mechanical and thermal factors needed for co-designing advanced packaging for high power. The outline of this post is as follows:

• I will explain the current I-shaped paradigm in most technology companies and why engineers will need to embrace T-shaped skillset to effectively co-design tightly integrated systems

• I’ll discuss the key challenges that GPUs are placing on both the package and circuit side

• Then I’ll discuss two fundamental concepts and associated material properties for successful co-design of sub-components with advanced packaging:

  • Thermodynamics, including the three sources of heat transfer and thermal resistance

  • Stress-strain and associated material properties such as CTE

• Then I’ll describe the:

  • 🔒Three main sources of warpage

  • 🔒Four common failure modes

  • 🔒Challenges with modelling cross coupling failure modes

• 🔒Last, I’ll discuss a few warpage mitigation options

The research from this post comes from both from my conference experience at ECTC and the book “Hybrid Bonding, Advanced Substrates, Failure Mechanisms, and Thermal Management for Chiplets and Heterogeneous Integration” (2025). I found this book to be a useful mix of both high-level fundamental overviews of advanced packaging and current in-the-weeds academic research on key areas related to packaging.

I previously wrote a masterclass post on the fundamentals of advanced packaging that covers what packaging “is”. This post builds off that by covering the physics dimension when it comes to CTE, warpage, and failure modes. I recommend you read that post along side this one to build a more complete view of advanced packaging.

First I want to describe what I believe effective hardware co-design requires.

A New Approach for Hardware Co-Design: The T Shaped Engineer

Currently, most engineers at major tech companies operate in the “I” shaped paradigm where engineers are highly specialized in their field of choice, and interface with other engineers through requirement specifications and handoff at interfaces.

As systems start become more tightly coupled across domains, many leaders are calling for more cross domain awareness and co-design. However, I believe that most engineers in the “I” shaped paradigm treat co-design as more frequent and earlier meetings.

I believe that effective co-design requires you to become more ‘T” shaped, that is, depth in one domain and breadth in others. This requires you to build a semi-independent knowledge base of high level concepts in other domains to be able to intuitively assess how factors from your domain affect others. This allows you to anticipate issues and ask key questions from domain experts early on.

Becoming T shaped is actually quite difficult to do in an I shaped paradigm, both cognitively and organizationally. Vikram Sekar described these challenges best when he gave career advice because often times, it might be possible to “step” on adjacent teams who are CTA.

I totally understand this, and I’m not saying you should ignore your orgs politics. In any case, here is my blueprint for people who want to become more “T” shaped:

Ground yourself in fundamental tradeoffs in silos adjacent to your domain of expertise

Effective co-design across multiple domains requires you to first ground yourself in the fundamentals of domains that relate to each other in some way. This requires deep work to analyze the technical fundamentals in domains adjacent to your own.

For me, the bulk of my co-design posts revolve around four interconnected domains in hardware:

• On-chip mixed signal (SerDes architecture, ADC, PLL)

• High speed communications (Optical, high speed wireline, and signal integrity)

• Power integrity / management

• Advanced packaging

Each specialty has their own unique set of tradeoffs, such as:

• Gain vs bandwidth in Analog

• Interconnect distance vs BER in SI

• Switching frequency vs ripple vs loss in Power

• Substrate area vs bump stress in Packaging

Understanding the fundamentals in each domains is not an easy process because it requires to you sort through domain specific knowledge from experts and try to extract out the important insights. I found that the tutorials at the beginning of the conferences are excellent at providing a framework to understand more complex conference material that build upon the tutorial material; these are what the tutorials are specifically made for. That way, when I read dense technical papers or conference digests, I can efficiently filter through information that doesn’t matter. I find that the bulk of the writing in conference papers is really dancing around the nuances of previous works while making claims of proposed solutions.

I’m not saying you should become an expert in domains outside of your own; that is overkill for practical purposes. However, I do think you should work backwards to figure out what baseline knowledge you need to understand more domain-specific knowledge from other people.

Understand how adjacent domains couple together

Then, after understanding tradeoffs in each domain, try to understand how effects from each domain “couple” to other domains. Based on my previous writing, these are some interactions I can think of off the top of my head:

• Power supply induced jitter and crosstalk lower BER of the signal path

• Fast current transients in AI workloads cause localized joule heating that can worsen reliability

• Ring modulators in optical communications are sensitive to thermals that need to be corrected with heater feedback loops

Understanding interactions is quite tricky that I admittedly don’t really understand fully quite yet and am trying to understand better myself.

My advice: start small and teach others

As a start, I recommend people first ground themselves in ONE field. Power and packaging are excellent interdisciplinary fields to start for anyone involved in semiconductors in anyways. I have several posts that provide a good starting point.

Then, to really test if you have the knowledge, try to teach it to others, whether that be through writing or a seminar. This way, others can mutually benefit from the insight in your own process of becoming more T shaped. It’s quite easy to fool yourself in thinking you know something from reading someone’s article until you go and sit down and explain that topic to another person.

The Co-Design Problem: High Power Density Stresses the Package

GPU roadmaps are projecting a huge increase in computational power that comes with higher performance requirements, including:

• High power usage. GPUs draw huge current density that is lost in the PDN and dissipates heat.

• High transient response. The critical frequency band of AI workload transients is between ~0.1-10 MHz, and the PDN needs to provide low enough impedance at these frequencies to meet the on-chip droop specs. This is typically done by placing localized decoupling capacitors as close to the chip as possible.

• Large Area. More GPUs per package increase the package area that increases the Distance to the Neutral Point (DNP).

To meet these performance demands, innovations are both needed on the package and circuit design side.

On the circuits side, much work has been done on optimizing specialized power conversion topologies such as multi-phase buck/TLVRs at the PoL and LLC DCX for the IBC. I dive deep into these fundamentals of the circuit architectures in more detail:

On the packaging side, there are several well established failure mechanisms and integration techniques. I briefly touched upon these in these posts:

The issue with high power is that they stress the package, enhance the already established failure mechanisms, and opens up possibilities for new ones. Large BGAs with up to 2000 - 6000 balls face mechanical challenges with heavy heat sinks and continuous vibration.

Lets dive deeper into important packaging considerations.

Fundamental Thermal and Mechanical Concepts: Thermodynamics and Stress-Strain

Co-design of the high power with the package involves knowledge of fundamental concepts in thermodynamics and stress-strain. These are pretty well known to people in those domains and I realize there’s a lot more depth underneath these equations I am simplifying.

As an EE myself who is more specialized on the circuit side, I’m framing these as high level mental models for people outside of these domains to have a first order understanding of the mechanical and thermal effects of packaging.

Likewise, if you are very familiar with these but not familiar with those concepts on the electrical side like signal integrity, power electronics, or the intricacies of high speed SerDes, well, lucky for you, I have mental models on those on my Substack as well that are linked throughout this post.

The Three Sources of Heat Transfer

Conduction

Conduction is heat transfer within a stationary solid, liquid or gas due to temperature differences. Energy is “diffused” from more energetic regions to less energetic particles.

Conduction is governed by Fourier’s law:

where

• q′′ is the heat transfer per unit area (W/m² )

  k is the thermal conductivity of the material (W/m K)

  dT/dx is the temperature gradient (K/m)

Common values for thermal conduction range from:

• 0.024 (air),

• ~0.2 - 0.35 (for epoxy, polymide, and FR4)

• 120 (silicon)

• 390 (copper)

Conduction matters when dissipating heat from:

• The GPU - Rubin generates 1,800W to 2,300W per GPU

• Joule heating in the interconnects - this is self-heating due to IR drop that increases as current density increases

Convection

Convection refers to heat transfer between a surface and a moving fluid at different temperatures

Convection is governed by Newtons laws of cooling:

where

• q′′ is the heat transfer per unit area (W/m²)

  h is the convective heat transfer coefficient (W/m² K)

  Ts is the surface temperature of the solid (K or ⁰C)

  Tinf is the temperature of the surrounding fluid far form the surface (K or ⁰C)

Convection can be classified either as free (such as hot air rising from a heater) or forced (such as cooling a CPU with a fan).

Common values for convective heat transfer coefficient include:

• Free: 2 - 25 for gasses and 1000 for liquids

• Forced: 25 - 250 for gasses and 100 - 20,000 for liquids

Convection cooling can be facilitated through the use of heat sinks, liquid cooling or immersion cooling with single and two phase variants.

Radiation

Radiation is the transfer of thermal energy through EM waves without a need for a medium. It is governed by:

where

• E is heat transfer rate of emission (W)

• ε is the emissivity of the surface (between 0 to 1)

• σ is the Stefan-Boltzmann constant (5.67e-8 W/m² K⁴)

• A is the surface area of the radiating body

• T_s is the absolute temperature of the surface (K or ⁰C)

Compared to conduction and convection, radiation is not a primary heat transfer mechanism for ground based AI data centers, but could potentially be a dominant heat mechanism for space based AI data centers. We’ll see how that plays out.

Note that radiation also includes the absorption of incident radiation, so the net heat transfer depends on the balance between the inflow and outflow of radiation.

Conduction and convection must be in balance for ground based AI data centers

Fundamentally, for a GPU to maintain a thermal equilibrium below a threshold temperature, the conduction and convection equations must be in balance with each other for the cooling system to handle the heat dissipation of the GPU and subsystems.

Of course, there are many other factors such as boundary conditions, unique material properties, and CPU loads that are important and must be taken into account. If, for whatever reason, the heat removal becomes a bottleneck of GPU performance, then tricks need to be played on the SW side to manage the workload until the cooling or packaging system is able to catch up.

Thermal Resistance

Thermal resistance quantifies the opposition to heat flow at any two points where there is a temperature difference. It is given by

where

• R_th is the thermal resistance (K/W or ⁰C/W)

  ∆T is the temperature difference between two points (K or ⁰C)

  q is the heat transfer rate (W)

Thermal resistance is a convenient first order approximation because it almost resembles an Ohms law analogy to heat transfer, with analogous parameters:

• Electrical current is the heat transfer rate

• Electrical resistance/conductivity is thermal resistance/conductivity

• Electrical potential is the temperature

Heat sink fins can be modelled approximately using this model to estimate heat transfer. Of course, this approximation is valid if the thermal “circuits” are contained within a lumped approximation, where the heat flow is uniformly distributed in confined materials. Anything that is distributed or highly coupled will require sophisticated modelling.

Stress-Strain

All materials with a PCB stack experience strain / material deformation under some kind of loading. There are two major categories of materials:

• Ductile material - A material that initially deforms linearly as more stress is applied, then after a certain threshold, it undergoes plastic deformation over a wide range until it ultimately fails. This is the dynamic when you pull hard taffy or gum. Most metals fall into this category.

• Brittle materials - Brittle materials show a steep linear curve with a sharp fracture at the top. Glass falls into this category.

For ductile material, the left most region is governed by Hookes law which describes material deformation in the elastic region. It is given by

where

• σ is the average normal stress across a cross section area of a material

• ε is the average normal strain, give by (L - L0) / L0

• E is the modulus of elasticity (or Youngs modulus)

On the right side of the linear region, the material starts deforming and ultimately fails to a fracture. Of course, we hope that packaging materials don’t enter this region, but performance requirements can make it difficult to design around this.

Another form of strain, shearing, changes the angle between two normally perpendicular lines of a material. It is given by:

Bumps in between package layers experience both shearing and compressive / tensive forces.

There are a few material properties that matter:

• Youngs modulus - Describes the ability for a material to resist deformation when subjected to stress. Typical values include:

  • 6 for underfill epoxy

  • 8 - 22 for FR4

  • 131 for silicon

  • 132 for copper

• Poisson’s ratio - the ratio of the strains in the axial direction and the lateral direction. The max value is 0.5. Typical values include:

  • 0.1 - 0.14 for FR4

  • 0.28 Silicon

  • 0.35 for copper

• Creep - a time dependent permanent deformation of a material under a constant load or stress at a constant temperature. Creep is common at elevated temperatures.

• Stress relaxation - a gradual decrease in stress by a material under a constant strain over time.

• Viscoelasticity - a nonlinear, hysteretic curve to loading and unloading where a material recovers its shape over time after unloading

• Viscoplasticity - when a material suffers permanent, rate-dependent plastic deformation that does not recover

  • Viscoplasticity is important when describing the behavior of solder since it is subject to strain and creep deformation.

  • One popular viscoplasticity model of solder is the Anand model that governs the rate of change of the inelastic strain. It takes multiple effects such as strain rate sensitivity and deformation resistance into account.

• Coefficient of Thermal Expansion (CTE)

  • CTE is perhaps one of the most important and most talked about material properties for packages because it describes material behavior at the interface of thermal and mechanical properties.

  • CTE is a form of material “strain” where an increase in temperature causes the material to expand, and a decrease causes it to contract. It is given by:

    

    where

    • εth is the strain due to temperature with no mechanical load

      α is the coefficient of thermal expansion

      ∆T is the change in temperature

  • Common CTE values include:

    • 2.6 for silicon

    • 17 for copper

    • 20, 70 for epoxy

    • FR4:

      • 10, 15 in plane

      • 65, 180 in z-axis

  • For any given package size, material with a higher distance from the neutral point will experience higher deformation since it elongates / contracts more, thus increasing the stress on solder joints in that area.

Warpage

Now that I've established some thermal and mechanical fundamentals, we can discuss how these play a role in warpage, and failure modes after the paywall.

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Editors Note (6/22/26) - I am paywalling the last half of this post and rearranging the post outline at the beginning.

Before the paywall, I link several of my other posts in adjacent domains in power electronics, high speed communications, and signal integrity that related to packaging in some way.

In this post I’ll build intuition of the key tradeoffs and constraints surrounding advanced packaging.

• I’ll define each of the classifications at a high level (from 2D to 3.5D)

• Then I’ll do a breakdown of each of the key options of a TSMC 2.5D CHIP on WAFER on SUBSTRATE (CoWoS). We will examine this package architecture through the following lens:

  • TSV Fabrication

  • RDL Fabrication (with BEOL Process for Si)

  • Interconnect Options (C4 Bump, C2 Cu Pillar)

  • 🔒Substrate Options

    • 🔒Glass Substrate and the unique challenges: SeWaRe and bump reliability

    • 🔒Panel or Wafer - Why we didn’t do panels in the first place

    • 🔒Embedded bridge in Organic Substrate

      • 🔒TSMC CoWoS-L vs Intel EMIB-T

  • 🔒The Process Steps for Hybrid bonding and why it isn’t widely adopted

The reason I write this post is to establish some fundamentals of advanced packaging and communicate what a packaging engineer would like other engineers to know who are interfacing with packaging. My goal is to build on top of the knowledge on this post as well as my existing posts to be able to understand how to properly co-design electronics with the package.

Please note that I do not consider myself an expert in advanced packaging by any means. I reference John Lau’s slides from his seminar at ECTC 2026 and my overall conference experience to better understand the interactions with advanced packaging and other domains.

If you’re an expert and notice something incorrect, please reach out to me so I can have it promptly corrected.

Before I wrote this, I touched upon high level packaging issues regarding reliability, multiphysics simulation, and co-packaged optics in this post I wrote shortly after I attended ECTC 2026:

Advanced Packaging is like City Planning

Advanced Packaging is a lot like city planning:

• In rural areas, houses and buildings are distributed across a large plot of land (2D)

• In suburbs, houses and mid-sized buildings are bundled closer together and connected (2.1, 2.3, 2.5D)

• In cities, floors are stacked both above and below with means to access them (3D, 3.3D, 3.5D)

City planning is all about managing the flow of people to and from desired destinations.

Advanced packaging follows the same logic: signals need to get to and from compute devices. However, there is an an order of magnitude difference between the dimensions of the on-chip interconnect and the PCB/package interconnect. As speed and power requirements increase, more sophisticated and elegant means of package interconnect are needed to bridge this order of magnitude difference.

Just like any building, as you start stacking floors, the structural stability needs to be considered with appropriate safety factors designed in. This logic also applies to advanced packaging as factors like reliability, thermal, and mechanical characteristics become more important.

High Level Classifications: From 2D to 3D

There are several structural variants of advanced packaging. All of these build the system on top of a build-up package substrate on top of a PCB.

Why do you need a buildup package substrate? There are a few reasons:

• Package substrates help “bridge” the dimensional order-of-magnitude gap with the chip level interconnects and the board level traces. This is done through “fan out connections” where the package solder balls spread the signals out from underneath a chip.

• Mechanical Buffer. The package acts as a buffer to protect the chip against stress, vibration and thermal effects. The coefficient of thermal expansion is an important consideration. We’ll see how, quite paradoxically, the low CTE of glass can have a negative impact on reliability.

• Local interconnect amongst amongst chiplets. This is done through a combination of Re-distribution layers (RDLs) and Back-end-of-line (BEOL) metallization on Si Wafers

2D Integration

2D packaging represents the historical and architectural “baseline” packaging technology that more advanced variants build off of. In 2D we have the following classifications:

• 2D - the chip is bonded directly on top of a build-up package substrate.

• 2.1D - the RDLs (Redistribution Layers) are built as thin film layers directly on top of the organic substrate itself.

• 2.3D - The RDLs are fabricated separately on an organic interposer on top of a build-up package substrate. This is also known as the “hybrid approach”.

• 2.5D - The chips themselves sit directly on top of a massive, monolithic Silicon Core (Silicon Interposer) or a Glass Core (Glass Interposer)

In 2.1D and 2.3D, two popular materials used in the dielectric films are ABF and PID.

• Ajinomoto Build-Up Film (ABF) is a resin-based epoxy film embedded with silica fillers.

  • ABF has exceptional mechanical stability, excellent thermal resistance, and a low Coefficient of Thermal Expansion (CTE)

• Photoimageable Dielectric (PID) is almost chemically similar to photoresist; it is a liquid polymer or dry film that is chemically engineered to react directly to light.

  • PID can be made much finer than ABF, but is traditionally mechanically weaker than ABF.

There is a core mechanical stability vs feature size tradeoff between both films. ABF tends to be the dominant choice of packaging due to its ability to handle many metal layers.

2.1D / 2.3D are considered to be low cost alternatives to 2.5D, which is considered the standard for AI/HPC.

3D Integration

3D enables more computational density to be stacked in the vertical direction. The higher order classifications in 3D are still emerging and contested, but this is what Lau preliminarily defines:

• 3D - stacking chiplets directly on top of each other vertically on an active interposer (compared to 2.5D which is passive). These active interposers can contain IVRs, NoCs, BIST, or other peripheral circuitry that complement the functions of the SoC.

• 3.3D - consists of HBM on top of an SoC without a TSV interposer

• 3.5D - Involve hybrid bonding chiplets before integrating heterogeneously all components onto a single substrate.

As packages becoming increasingly integrated with the chip themselves, this leads to one of the biggest packaging challenges: whose responsibly should be for final assembly of the packaging: the fab, or the OSAT? Historically, both fab and OSAT specialized in different parts of the semiconductor production flow. The fab specialized in short pitch, finer interconnects and the OSAT specialized in higher pitch, coarser interconnects.

When hybrid technologies such as bridges and LSI in organic substrates come along, who will assume responsibility for final package integration? This is a question that is still being fiercely debated among the fab and packaging community and will be left for another time.

A Package Teardown: 2.5D

In the next section we will do a deep dive into the fabrication process of 2.5D and examine the fabrication process for each part. 2.5D is considered the package of choice for HPC due to its form factor and performance. For example, the NVIDIA H100 “Hopper” GPU uses this package and a cross section shows key features between the build-up package substrate and logic.

TSV Fabrication

A through-silicon via (TSV) transports signals and power completely through the thick structural floor (the raw Silicon Substrate). In CoWoS, the diameter is ~ 5-10um and the pitch is ~40-50um.

Lets go through the process steps:

• First, we start with standard lithography to add SiO2 on the Si surface that acts as the “hard mask” for TSV:

  • Deposit SiO2 by thermal oxidation of Plasma-Enhanced Chemical Vapor Deposition (PECVD)

  • Apply Photoresist

  • Pattern with lithography through a photo mask

  • Etch the SiO2

• After the SiO2 is deposited, the via hole is formed using Deep Reactive Ion Etching (DRIE). The most commonly used process is the Bosch process.

• After this hole is formed, it is filled with copper:

  • An SiO2 layer is added with PECVD/Sub-Atmospheric CVD to act an an electrical insulator against Si and Copper

  • Then, a barrier (Ti/Ta) and seed (Cu) added to prevent copper poisoning

  • Then, the hole is filled with copper, annealed to stabilize the grain structure, and polished with CMP.

Important thing to note: The more power TSVs you add to feed a power-hungry GPU, the more you “choke” the horizontal routing channels available for the RDLs to connect the GPU to its HBM memory.

RDL Fabrication

Then the RDLs are fabricated on top of the TSV using Standard BEOL Processes using dual damascene. Dual damescene refers to etching both the via and horizontal line trench before adding any metal. Heres how it works:

• Form the via and M1 trenches with standard lithography. This is the same process as with TSVs: Deposit SiO2 with PECVD + photoresist on top, etch the photoresist then the oxide

• Line trenches with a thin Ti/Cu seed layer with PVD

• Overfill the whole trench with electroplated copper

• Polish the excess copper on the surface with CMP to give you a planar surface

Compared to standard packaging methods that limit pitch to 2-5um, this method can get down to 0.4um (at the time of writing this paper).

A passive silicon interposer typically features 4 to 6 BEOL metal layers on the front-side (top), and 2 to 4 coarser packaging RDL layers on the back-side (bottom).

As more layers are added, film stress is added. With HBM4, foundries like TSMC and UMC are actively extending front-side BEOL capabilities to 8, 9, or 10 layers to accommodate the massive explosion of traces.

Interconnect Options

Bumps are formed by first forming an under/bump metallization with both a thin barrier layer (Titanium, tungsten, chromium) and seed layer (Copper/nickel). There are two major categories of bumps:

• C4 (Controlled Collapse Chip Connection):

  • C4 bumps are great for macro power delivery and board-level packaging

  • However, the pitch of C4 bumps are limited to 50-150um because they can cause “solder bridging” if they are too close

• C2 Pillar

  • The actual solder is just a tiny cap sitting on top of a rigid, electroplated copper that does not melt during reflow

  • These allow you to jam interconnects much closer together, but are much more expensive, primarily due to plating time of the Cu pillars

The other major option is Hybrid Bonding, which I’ll discuss at the end.

At higher current densities, both bump resistance and CTE affect reliability. I noticed a few posters at ECTC that demonstrate how a few small effects can magnify:

• Bumps further from the neutral point of a chip experience more deformation as substrate/chip area get larger

• The direction current flows into and out of the bump affects the equivalent resistance of the bump by a few percentage points

• The elemental composition at the bond interface can affect current density as well.

At higher current densities, these effects can lead to localized joule heating that can create “hotspots” and can increase the probability of failures.

Substrate Options

Silicon substrates are great for fabricating the fine pitch interconnect needed in between chiplets. However, silicon substrates are running into a few problems:

• They are expensive

• Fabrication is limited to major IDMs

• Substrates are running into photolithography reticle size limits

• Silicon everywhere is frankly overkill when the fine pitched interconnect is limited to specific areas in between chips.

After the paywall, I’ll discuss the following:

• Two alterative options to silicon: Glass and organic with bridges.

• Panels vs wafers, and why we didn’t do panels in the first place

• A brief history of hybrid bonding, the mechanism, and why its not widely adopted yet

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Here are several of my other posts I’ve written that provide the technology fundamentals of power, high speed communications, and AI compute that packaging is the physical container for.

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Editors Note (6/22/26) - I am paywalling the last half of this post. Before the paywall, I link several of my other posts in adjacent domains in power electronics, high speed communications, and signal integrity that related to packaging in some way.

In this post I discuss the following topics:

• Clear definitions of five buzzwords used in advanced packaging from John Lau’s tutorial

• How Reliability is one of the biggest concerns for engineers on the floor

• 🔒The Wild West of Co-packaged optics - Different CPO Integration Options

• 🔒Why Multiphysics simulation is not that easy in practice

Hardware is becoming the new bottleneck in hyperscalers.

That was was the underlying message at ECTC 2026, the flagship electronics packaging conference, as stated in a plenary session by Dr. Tien Wu, CEO of Advanced Semiconductor Engineering, the largest OSAT in the world.

I attended ECTC 2026, not as a pure packaging engineer, but as a Analog/Mixed signal system architect who is curious about how advanced packaging is interrelated with other elements.

Before I came to this conference, I went in knowing a bit about advanced packaging from other writers. I studied mixed signal architectures in high-speed communications and power systems through self-directed conference travel to ISSCC, DesignCon, and APEC. I wrote comprehensive architecture breakdowns specifically to bring awareness to key constraints so that engineers can ask more informed questions earlier in the design process. I wrote about why I am doing this in my post:

As an EE myself, we sometimes take packaging for granted. However, ECTC made me realize the sheer amount of depth and mechanical considerations that go into packaging. The performance demands of GPUs are placing a lot of stress on the packaging itself and shifts the bottleneck toward hardware, not software, as the limiting factor in scaling AI compute performance.

In this post I’ll give a very broad high level overview of my experience at ECTC and the key challenges engineers on the floor are facing.

John Lau Tutorial on Advanced Packaging

At the beginning of the conference, I acquainted myself with advanced packaging trends through a tutorial given by John Lau. He is considered a legend in the packaging community because he wrote virtually every major book on advanced packaging and heterogeneous integration. He is very practical and as close to the manufacturing reality. His lecture was an experience; he tends to “beat” concepts into your head through repetition; I am not joking. I felt like I passed through a rite of passage.

He broke down the classifications (2D, 2.1D, 2.3D, 2.5D, 3D, 3.5D) as shown in the figure above, as well as described key issues in hybrid bonding and glass substrates. These topics are covered quite extensively by other writers and I will not go into depth here.

He notes that several terms in advanced packaging are often misused. He clearly defines these terms as the following:

He is also well versed in the second-order effects of manufacturability. He mentioned how larger panel sizes (600x600mm) that pack more parts per panel are not always better because it takes longer for the pick and place machine to traverse the distance to move the parts between panel and product.

After the seminar, I personally ordered up a book myself “Hybrid Bonding, Advanced Substrates, Failure Mechanisms, and Thermal Management for Chiplets and Heterogeneous Integration” (2025) to understand the interactions between advanced packaging and adjacent domains. I anticipate this book will strike a balance in describing the interactions with advanced packaging with other domains and will be a valuable resource. I’ll use the material in this book to inform my future writing.

In my view, there is a ton of noise and hype around advanced packaging. At the end of this post, I’ll also list some advanced packaging books by John Lau so that if you’re deciding to write or understand this space better, you have a source of truth to reference.

Two of the major ones high volume advanced packaging techniques are TSMC CoWoS and Intel EMIB, and is clear that Intel is becoming popular as supply chain bottlenecks for CoWoS are coming into play.

Reliability is one of the biggest concerns for engineers on the floor

Most people out there hyperfocus on the raw performance metrics of the GPUs, CPOs, the potential of hybrid bonding and glass substrates, or what Jensen is doing; they are clearly some of the flashiest subjects.

However, as GPU power increases demand more power and signal speed, these effects put more stress the package and “magnify” the existing failure mechanisms! Reliability is especially a concern as package sizes get bigger; they get heavier and introduce more points of failure.

Reliability is something historically thrown over the wall in the semiconductor industry as basically a cost center with a “line” to hit.

I was quite surprised by how much reliability was discussed among the conference among special sessions and technical sessions. There were a new notable observations amongst panelists in the special sessions:

• Tsun-yen Wu (in place of Kathy Yan), Department Manager at TSMC, pointed out two things:

  • First, there is a tradeoff between four domains in packaging:

    • Routability

    • Crosstalk (NOTE: This doesn’t appear correct; to first order, when spacing goes down, crosstalk goes up since there there is higher capacitance between the lines. However, lower line width decreases the fringing capacitance as well, so overall crosstalk depends on the dimensional scaling factors and also ground shielding used)

    • Structure stress/tension

    • Process difficulty

  • He also notes that many package designers tend to design their packages aggressively and not taking manufacturability into consideration early in the design, such as stacking as many vias as possible. This requires constant back and forth to ensure the package is manufacturable. This wastes communication time, especially across time zones, if a working knowledge of reliability is not known by packaging designers beforehand.

• Dr. Richard Rao, Distinguished Engineer at Marvell, notes that transient switching can cause stress, and that a change from a stress strain approach to fracture mechanics approach is needed.

• Gang Duan, EVP, Samsung, points out that embedding components in substrate is aggressive and can affect yield and performance

• Dr. Choong Un Kim, Professor, Material Science at UT Arlington, points out that joule heating leads to local stress which leads to cracking

I also learned of several failure mechanisms in advanced packaging. Here are a few examples:

Much like how we personally take reliability into account when we buy a car, investors and engineers should also take reliability of systems into account. You can have a well performing part or tightly integrated system that generates buzz, but if it causes you reliability problems down the line, it might not be the best long-term solution.

I do think reliability engineering will become much more important than ever, or at the very least, a topic board level engineers MUST know as systems become more tightly integrated. I think that reliability training will go a LONG way to help minimize the cost of constant back and forth as systems become more tightly integrated.

I dive into more depth regarding the fundamental structures and physics behind these failure modes:

The Wild West of Co-packaged optics

Co packaged optics is one of the hottest, yet diverse, topics of the conference. CPO consists of three major blocks:

• Photonic IC (PIC) - This consists of the photonic IC such as photodiode, laser, etc.

• Electrical IC (EIC) - This consists of the electrical circuits such as the transimpedance amplifier (TIA), laser driver, etc.

• Application-specific IC (ASIC) Switch

There are a number of clear performance advantages of CPO that make it such an attractive option compared to pluggable transceivers, such as lower length, reducing energy to drive the signal, and lower latency. Many content creators have written exhaustively on this.

Though the physics of devices themselves can be a bit tricky, the architecture behind optical communications has a simple mental model:

• You have a laser source that is routed through a PIC.

• This laser is generated from a VCSEL, micro led, or other laser source.

• Then, this laser source is modulated externally with either a MZM, micro-ring, or electro absorption modulator from a high frequency signal from an EIC.

• This signal is sent through the optical channel at a particular “band” (850n, O,C,L), detected with a photodiode, and amplified with a trans-impedance amplifier.

I cover these in more detail in my other posts:

What makes co-packaged optics so interesting and yet confusing are the vast amount of packaging techniques involved. Each system has a own unique set of requirements for high speed data rates, system constraints, and a power/ BER link budget to handle.

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For instance, here are a few options for 2D CPO structures with bridging and bumping techniques:

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